Semiconductor device with improved protection from electrostatic discharge

• US 20050035416A1
• Filed: 09/23/2004
• Published: 02/17/2005
• Est. Priority Date: 03/11/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Katsuhito Sasaki, Toshikazu Kuroda
• Inventors: Kuroda, Toshikazu, Sasaki, Katsuhito
• Granted Patent: US 7,238,991 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

Claims

1-6. -6. (Canceled)

7. A semiconductor device having a semiconductor substrate covered by an oxide film, the semiconductor device comprising:

a gate electrode formed on the oxide film, having an annular polygonal shape with exterior sides, interior sides, and interior corners;

a plurality of source diffusions formed in the semiconductor substrate, disposed facing and extending beneath respective exterior sides of the gate electrode; and

a drain diffusion formed in the semiconductor substrate, the drain diffusion having a polygonal shape with exterior sides and deleted corners, the exterior sides of the drain diffusion being disposed facing and extending beneath the interior sides of the gate electrode but avoiding the interior corners of the gate electrode.

8. The semiconductor device of claim 7, further comprising a guard ring diffusion formed in the semiconductor substrate, the guard ring diffusion having an annular shape surrounding the source diffusions.

9. The semiconductor device of claim 8, wherein the semiconductor substrate is a semiconductor of a first conductive type, the source diffusions and drain diffusion are diffusions of a second conductive type, and the guard ring diffusion is a diffusion of the first conductive type.

10. The semiconductor device of claim 9, further comprising a first metal interconnection pattern coupling the source diffusions to a power-supply or ground potential, whereby the semiconductor device provides protection from an electrostatic discharge conducted to the drain diffusion.

11. The semiconductor device of claim 10, wherein the first metal interconnection pattern also couples the gate electrode to the power-supply or ground.

12. The semiconductor device of claim 10, further comprising a second metal interconnection pattern coupling the drain diffusion to an input or output lead of an integrated circuit in which the semiconductor device is a circuit element.

13-18. -18. (Canceled)