Device with low-k dielectric in close proximity thereto and its method of fabrication

• US 20050035455A1
• Filed: 08/14/2003
• Published: 02/17/2005
• Est. Priority Date: 08/14/2003
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tang, Denny, Hu, Chenming, Tseng, Horng-Huei
• Application Number:
  US10/640,312
• Publication Number:
  US 20050035455A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A semiconductor device with a low-k material in close proximity thereto and its fabrication method. The device includes a gate electrode overlying a substrate. An electrically conductive plug is provided immediately adjacent to the gate electrode and making electrical contact to the device. A low-k dielectric material is disposed in the space between the gate electrode and the electrically conductive plug whereby reducing the parasitic capacitance. Thus, higher density of devices can be formed without decreasing operating speed.

Claims

1. A semiconductor device, comprising:

a substrate;

a device having a gate electrode overlying the substrate;

an electrically conductive plug adjacent to the gate electrode and making electrical contact to the device;

a buffer layer overlying the device and the substrate; and

a low-k dielectric material disposed in the space between the gate electrode and the electrically conductive plug.

2. The semiconductor device as claimed in claim 1, wherein the device comprises a MOS transistor.

3. The semiconductor device as claimed in claim 1, further comprising a gate dielectric having an effective thickness less than 25 Å

interposed between the gate electrode and the substrate.

4. The semiconductor device as claimed in claim 1, wherein the substrate comprises defective semiconductor lattice.

6. The semiconductor device as claimed in claim 1, wherein the substrate comprises silicon and germanium.

7. The semiconductor device as claimed in claim 1, wherein the height of the gate electrode is less than about 3,000 Å

.

8. The semiconductor device as claimed in claim 1, wherein the width of the gate electrode is less than about 1,000 Å

.

9. The semiconductor device as claimed in claim 1, wherein the dielectric constant of the low-k dielectric material is less than about 3.3.

10. The semiconductor device as claimed in claim 1, wherein the dielectric constant of the low-k dielectric material is less than about 2.8.

11. The semiconductor device as claimed in claim 1, wherein the low-k dielectric material comprises fluorosilicate glass (FSG), Black Diamond, an organic spin-on material, a spin-on-glass (SOG) material, an inorganic CVD material, or combinations thereof.

12. The semiconductor device as claimed in claim 1, wherein the low-k dielectric material comprises a carbon-containing material.

13. The semiconductor device as claimed in claim 1, wherein the low-k dielectric material comprises a carbon/oxygen-containing material.

14. The semiconductor device as claimed in claim 1, wherein the spacing between the gate electrode and the electrically conductive plug is less than about 2,000 Å

.

16. The semiconductor device as claimed in claim 1, wherein the buffer layer is a silicon/nitrogen-containing film.

17. The semiconductor device as claimed in claim 1, wherein the buffer layer functions as an etch stop layer and comprises a material of nitride doped silicon oxide, silicon nitride, or silicon-rich oxide.

18. The semiconductor device as claimed in claim 1, wherein the buffer layer functions as a diffusion barrier and comprises a material of carbon doped silicon oxide, carbon-doped silicon carbide, silicon carbide, or silicon-rich oxide.

19. The semiconductor device as claimed in claim 1, wherein the buffer layer functions as an adhesion layer and comprises a material of carbon doped silicon oxide, carbon-doped silicon nitride, silicon carbide, or silicon-rich oxide.

20. The semiconductor device as claimed in claim 1, wherein the width of the electrically conductive plug is between about 100 and 1000 Å

.

21. The semiconductor device as claimed in claim 1, wherein the low-k dielectric material substantially fills the space between the gate electrode and the electrically conductive plug.

128. The semiconductor device as claimed in claim 1, wherein the buffer layer has a thickness between about 200-2000 Å

5. (Canceled)

15. (Canceled)

22. A semiconductor device, comprising:

a substrate;

a device having a gate electrode overlying the substrate;

a buffer layer overlying the substrate and the device;

a low-k dielectric layer disposed in close proximity to the device and overlying the buffer layer, wherein the low-k dielectric layer and the buffer layer define a contact opening adjacent to the gate electrode; and

an electrically conductive plug embedded in the opening and making electrical contact to the device.

23. The semiconductor device as claimed in claim 22, wherein the device comprises a MOS transistor.

24. The semiconductor device as claimed in claim 22, further comprising a source/drain region in the substrate adjacent to the gate electrode whereby the electrically conductive plug is disposed thereupon to make electrical contact to the device.

25. The semiconductor device as claimed in claim 22, wherein the low-k dielectric layer is present within 200 nm from the gate electrode.

26. The semiconductor device as claimed in claim 22, wherein the low-k dielectric layer is present within 200 nm from the source/drain region.

27. The semiconductor device as claimed in claim 22, further comprising a gate dielectric having an effective thickness less than about 50 Å

interposed between the gate electrode and the substrate.

28. The semiconductor device as claimed in claim 22, wherein the substrate comprises defective semiconductor lattice.

30. The semiconductor device as claimed in claim 22, wherein the substrate comprises silicon and germanium.

31. The semiconductor device as claimed in claim 22, wherein the height of the gate electrode is less than about 3,000 Å

.

32. The semiconductor device as claimed in claim 22, wherein the width of the gate electrode is less than about 1000 Å

.

33. The semiconductor device as claimed in claim 22, wherein the dielectric constant of the low-k dielectric layer is less than about 3.3.

34. The semiconductor device as claimed in claim 22, wherein the dielectric constant of the low-k dielectric layer is less than about 2.8.

35. The semiconductor device as claimed in claim 22, wherein the low-k dielectric layer comprises fluorosilicate glass (FSG), Black Diamond, an organic spin-on material, a spin-on-glass (SOG) material, an inorganic CVD material, or combinations thereof.

36. The semiconductor device as claimed in claim 22, wherein the low-k dielectric layer comprises a carbon-containing material.

37. The semiconductor device as claimed in claim 22, wherein the low-k dielectric layer comprises a carbon/oxygen-containing material.

38. The semiconductor device as claimed in claim 22, wherein the spacing between the gate electrode and the electrically conductive plug is less than about 2000 Å

.

40. The semiconductor device as claimed in claim 22, wherein the buffer layer is a silicon/nitrogen-containing film.

41. The semiconductor device as claimed in claim 22, wherein the buffer layer functions as an etch stop layer and comprises a material of nitride doped silicon oxide, silicon nitride, or silicon-rich oxide.

42. The semiconductor device as claimed in claim 22, wherein the buffer layer functions as a diffusion barrier and comprises a material of carbon-doped silicon oxide, carbon-doped silicon nitride, silicon carbide, or silicon-rich oxide.

43. The semiconductor device as claimed in claim 22, wherein the buffer layer functions as an adhesion layer and comprises a material of nitride doped silicon oxide, carbon doped silicon nitride, or silicon-rich oxide.

44. The semiconductor device as claimed in claim 22, wherein the width of the electrically conductive plug is between about 100-1000 Å

.

129. The semiconductor deice as claimed in claim 22, wherein the buffer layer has a thickness between about 200-2000 Å

.

29. (Canceled)

39. (Canceled)

45. A semiconductor device, comprising:

a substrate;

a device having a gate electrode overlying the substrate and a pair of source/drain regions formed in the substrate oppositely adjacent to the gate electrode, wherein the width of the gate electrode is less than about 1000 Å

;

a buffer layer overlying the device and the substrate;

a blanket low-k dielectric layer overlying the device and the substrate, wherein the low-k dielectric layer and the buffer layer define a contact opening to one of the source/drain regions; and

an electrically conductive plug embedded in the opening and making electrical contact to one of the source/drain regions, wherein the spacing between the electrically conductive plug and the gate electrode is less than about 2000 Å

.

46. The semiconductor device as claimed in claim 45, wherein the low-k dielectric layer is present within 200 nm from the gate electrode.

47. The semiconductor device as claimed in claim 45, wherein the low-k dielectric layer is present within 200 nm from the source/drain region.

48. The semiconductor device as claimed in claim 45, further comprising a gate dielectric having an effective thickness less than about 25 Å

interposed between the gate electrode and the substrate.

49. The semiconductor device as claimed in claim 45, wherein the substrate comprises defective semiconductor lattice.

51. The semiconductor device as claimed in claim 45, wherein the substrate comprises silicon and germanium.

52. The semiconductor device as claimed in claim 45, wherein the height of the gate electrode is less than about 3,000 Å

.

53. The semiconductor device as claimed in claim 45, wherein the dielectric constant of the low-k dielectric layer is less than about 3.3.

54. The semiconductor device as claimed in claim 45, wherein the dielectric constant of the low-k dielectric layer is less than about 2.8.

55. The semiconductor device as claimed in claim 45, wherein the low-k dielectric layer comprises fluorosilicate glass (FSG), Black Diamond, an organic spin-on material, a spin-on-glass (SOG) material, an inorganic CVD material, or combinations thereof.

56. The semiconductor device as claimed in claim 45, wherein the low-k dielectric layer comprises a carbon-containing material.

57. The semiconductor device as claimed in claim 45, wherein the low-k dielectric layer comprises a carbon/oxygen-containing material.

58. The semiconductor device as claimed in claim 45, wherein the spacing between the gate electrode and the electrically conductive plug is less than about 2000 Å

.

60. The semiconductor device as claimed in claim 45, wherein the buffer layer is a silicon/nitrogen-containing film.

61. The semiconductor device as claimed in claim 45, wherein the buffer layer functions as an etch stop layer and comprises a material of nitride doped silicon oxide, silicon nitride, or silicon-rich oxide.

62. The semiconductor device as claimed in claim 45, wherein the buffer layer functions as a diffusion barrier and comprises a material of carbon doped silicon oxide, carbon doped silicon nitride, silicon carbide, or silicon-rich oxide.

63. The semiconductor device as claimed in claim 45, wherein the buffer layer functions as an adhesion layer and comprises a material of carbon doped silicon oxide, carbon doped silicon nitride, or silicon-rich oxide.

64. The semiconductor device as claimed in claim 45, wherein the width of the electrically conductive plug is between about 100-1000 Å

.

130. The semiconductor device as claimed in claim 45, wherein the buffer layer has a thickness between about 200-2000 Å

.

50. (Canceled)

59. (Canceled)

65. A semiconductor device, comprising:

a substrate;

two closely spaced devices on the substrate, isolated with an isolation element therebetween;

two adjacent electrically conductive plugs disposed between the two closely spaced devices and respectively making electrical contact to each of the devices;

a low-k dielectric material having a dielectric constant less than about 2.8 disposed in the space between the two adjacent contact plugs; and

a buffer layer disposed between the substrate and the low-k dielectric material.

66. The semiconductor device as claimed in claim 65, wherein the devices comprise two closely spaced MOS transistors.

67. The semiconductor device as claimed in claim 65, wherein the isolation element is a trench isolation element.

68. The semiconductor device as claimed in claim 65, wherein the substrate comprises defective semiconductor lattice.

70. The semiconductor device as claimed in claim 65, wherein the substrate comprises silicon and germanium.

73. The semiconductor device as claimed in claim 65, wherein the low-k dielectric material comprises an organic spin-on material.

76. The semiconductor device as claimed in claim 65, wherein the spacing between the two adjacent electrically conductive plugs is less than about 2000 Å

.

77. The semiconductor device as claimed in claim 65, wherein the width of each of the electrically conductive plugs is between about 100-1000 Å

.

78. The semiconductor device as claimed in claim 65, wherein the low-k dielectric material substantially fills the space between the two electrically conductive plugs.

79. The semiconductor device as claimed in claim 65, wherein the width the isolation element is less than about 1500 Å

.

124. The semiconductor device as claimed in claim 65, wherein the buffer layer is a silicon/nitrogen-containing film.

125. The semiconductor device as claimed in claim 65, wherein the buffer layer functions as an etch stop layer and comprises a material of nitride doped silicon oxide, silicon nitride, or silicon-rich oxide.

126. The semiconductor device as claimed in claim 65, wherein the buffer layer functions as a diffusion barrier and comprises a material of carbon doped silicon oxide, carbon doped silicon nitride, silicon carbide, or silicon-rich oxide.

127. The semiconductor device as claimed in claim 65, wherein the buffer layer functions as an adhesion layer and comprises a material of carbon doped silicon oxide, carbon doped silicon nitride, or silicon-rich oxide.

131. The semiconductor device as claimed in claim 65, wherein the buffer layer has a thickness between about 200-2000 Å

.

69. (Canceled)

71. (Canceled)

72. (Canceled)

74-75. -75. (Canceled)

80. A method of manufacturing a semiconductor device, comprising the steps of:

providing a device having a gate electrode overlying a substrate;

forming a low-k dielectric layer in close proximity to the device;

forming a contact opening adjacent to the gate electrode through the low-k dielectric layer; and

forming an electrically conductive plug in the opening to make electrical contact to the device.

81. The method as claimed in claim 80, wherein the device comprises a MOS transistor.

82. The method as claimed in claim 81, wherein the device further comprises a source/drain region in the substrate adjacent to the gate electrode whereby the electrically conductive plug is disposed thereupon to make electrical contact to the device.

83. The method as claimed in claim 80, further comprising forming a buffer layer overlying the device and the substrate prior to forming the low-k dielectric layer.

84. The method as claimed in claim 83, wherein the buffer layer is a Si/N-containing film.

85. The method as claimed in claim 83, wherein the buffer layer functions as a diffusion barrier and comprises a material of SiOC, SiNC, SiC, or Si-rich oxide.

86. The method as claimed in claim 83, wherein the buffer layer functions as an adhesion layer and comprises a material of SiOC, SiNC, or Si-rich oxide.

87. The method as claimed in claim 83, wherein the buffer layer functions as an adhesion layer and comprises a material of SiOC, SiNC, or Si-rich oxide.

88. The method as claimed in claim 80, wherein the low-k dielectric layer is present within 200 nm from the gate electrode.

89. The method as claimed in claim 82, wherein the low-k dielectric layer is present within 200 nm from the source/drain region.

90. The method as claimed in claim 80, wherein the device further comprising a gate dielectric having an effective thickness less than about 25 Å

interposed between the gate electrode and the substrate.

91. The method as claimed in claim 80, wherein the substrate comprises defective semiconductor lattice.

92. The method as claimed in claim 80, wherein the substrate comprises silicon.

93. The method as claimed in claim 80, wherein the substrate comprises silicon and germanium.

94. The method as claimed in claim 80, wherein the height of the gate electrode is less than about 3,000 Å

.

95. The method as claimed in claim 80, wherein the width of the gate electrode is less than about 1000 Å

.

96. The method as claimed in claim 80, wherein the dielectric constant of the low-k dielectric layer is less than about 3.3.

97. The method as claimed in claim 80, wherein the dielectric constant of the low-k dielectric layer is less than about 2.8.

98. The method as claimed in claim 80, wherein the low-k dielectric layer comprises fluorosilicate glass (FSG), Black Diamond, an organic spin-on material, a spin-on-glass (SOG) material, an inorganic CVD material, or combinations thereof.

99. The method as claimed in claim 80, wherein the low-k dielectric layer comprises a carbon-containing material.

100. The method as claimed in claim 80, wherein the low-k dielectric layer comprises a carbon/oxygen-containing material.

101. The method as claimed in claim 80, wherein the spacing between the gate electrode and the electrically conductive plug is less than about 2000 Å

.

102. The method as claimed in claim 80, wherein the width of the electrically conductive plug is between about 100-1000 Å

.

103. The method as claimed in claim 80, wherein the low-k dielectric layer is blanketly formed overlying the substrate and the device.

104. A method of manufacturing a semiconductor device, comprising the steps of:

providing two closely spaced devices on a substrate, isolated with an isolation element therebetween;

forming a low-k dielectric layer overlying the two closely spaced devices; and

forming two adjacent electrically conductive plugs through the low-k dielectric layer between the two closely spaced devices to respectively make electrical contact to each of the devices.

105. The method as claimed in claim 104, wherein the devices comprise two closely spaced MOS transistors.

106. The method as claimed in claim 104, wherein the isolation element is a trench isolation element.

107. The method as claimed in claim 104, wherein the substrate comprises defective semiconductor lattice.

108. The method as claimed in claim 104, wherein the substrate comprises silicon.

109. The method as claimed in claim 104, wherein the substrate comprises silicon and germanium.

110. The method as claimed in claim 104, wherein the dielectric constant of the low-k dielectric material is less than about 3.3.

111. The method as claimed in claim 104, wherein the dielectric constant of the low-k dielectric material is less than about 2.8.

112. The method as claimed in claim 104, wherein the low-k dielectric material comprises fluorosilicate glass (FSG), Black Diamond, an organic spin-on material, a spin-on-glass (SOG) material, an inorganic CVD material, or combinations thereof.

113. The method as claimed in claim 104, wherein the low-k dielectric material comprises a carbon-containing material.

114. The method as claimed in claim 104, wherein the low-k dielectric material comprises a carbon/oxygen-containing material.

115. The method as claimed in claim 104, wherein the spacing between the two adjacent electrically conductive plugs is less than about 200 nm.

116. The method as claimed in claim 104, wherein the width of each of the electrically conductive plugs is between about 100-1000 Å

.

117. The method as claimed in claim 104, wherein the width the isolation element is less than about 1500 Å

.

118. The method as claimed in claim 104, further comprising forming a buffer layer overlying the device and the substrate prior to forming the low-k dielectric layer.

119. The method as claimed in claim 118, wherein the buffer layer is a Si/N-containing film.

120. The method as claimed in claim 118, wherein the buffer layer functions as a diffusion barrier and comprises a material of SiOC, SiNC, SiC, or Si-rich oxide.

121. The method as claimed in claim 118, wherein the buffer layer functions as an adhesion layer and comprises a material of SiOC, SiNC, or Si-rich oxide.

122. The method as claimed in claim 118, wherein the buffer layer functions as an adhesion layer and comprises a material of SiOC, SiNC, or Si-rich oxide.

123. The method as claimed in claim 104, wherein the low-k dielectric layer is blanketly formed overlying the devices, the substrate, and the isolation element.

132. A semiconductor device, comprising:

a substrate;

a device having a gate electrode overlying the substrate;

a low-k dielectric layer having a dielectric constant less than about 2.8 disposed in close proximity to but not contacting the gate electrode, wherein the low-k dielectric layer defines a contact opening adjacent to the gate electrode; and

an electrically conductive plug embedded in the opening and making electrical contact to the device.

133. The semiconductor device as claimed in claim 132, wherein the spacing between the gate electrode and the electrically conductive plug is less than about 2,000 Å

.

134. A semiconductor device, comprising:

a substrate;

a device having a pair of source/drain regions formed in the substrate oppositely adjacent to the device;

a low-k dielectric layer having a dielectric constant less than about 2.8 disposed in close proximity to but not contacting the source/drain regions, wherein the low-k dielectric layer defines a contact opening to one of the source/drain regions; and

an electrically conductive plug embedded in the opening and making electrical contact to the device.

135. A semiconductor device, comprising:

a substrate;

a device having a gate electrode overlying the substrate;

a low-k dielectric layer having a dielectric constant less than about 2.8 disposed in close proximity to but not contacting the gate electrode at a distance about 20-150 nm therefrom, wherein the low-k dielectric layer defines a contact opening adjacent to the gate electrode; and

an electrically conductive plug embedded in the opening and making electrical contact to the device.

136. The semiconductor device as claimed in claim 135, wherein the spacing between the gate electrode and the electrically conductive plug is less than about 2,000 Å

.

137. A semiconductor device, comprising:

a substrate;

a device having a pair of source/drain regions formed in the substrate oppositely adjacent to the device;

substrate oppositely adjacent to the device;

a low-k dielectric layer having a dielectric constant less than about 2.8 disposed in close proximity to but not contacting the source/drain regions at a distance about 20-150 nm therefrom, wherein the low-k dielectric layer defines a contact opening to one of the source/drain regions; and

an electrically conductive plug embedded in the opening and making electrical contact to the device.