Distributed write data drivers for burst access memories

• US 20050036367A1
• Filed: 09/22/2004
• Published: 02/17/2005
• Est. Priority Date: 12/23/1994
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Granted Patent: US 7,088,625 B2
• Time in Patent Office: Days
• US Class Current: 365/185.50
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.

Claims

1. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a IWE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal, wherein sequentially outputting two or more bytes from the memory device, comprises;

operating two or more output drivers in the memory device to drive a byte from the memory device onto data output pins coupled to the output drivers; and

continuing operation of the drivers to drive the byte onto the data output pins without tri-stating the data output pins during predetermined intervals of a strobe signal on at least one of an /RAS input pin and an /CAS input pin in the memory device.

2. A method of storing data in a system, comprising:

providing a first address from a microprocessor to a burst access memory;

providing a first data bit to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

3. The method of claim 2, wherein disabling the data driver enable circuits in response to asserting the equilibration signal comprises gating a version of the write enable signal with the equilibration signal.

4. The method of claim 2, wherein the recited steps are initiated in the recited order.

5. The method of claim 2, wherein providing the first address from a microprocessor to the burst access memory comprises inputting a single address to a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin.

6. A method of writing data into a memory device comprising:

providing an address for the memory device;

asserting an equilibrate signal to an equilibration device to equilibrate internal data lines of the memory device in response to providing the address;

communicating the equilibrate signal to a plurality of a data driver enable circuits located in close proximity and coupled to write data drivers;

communicating a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal;

driving data onto the internal data lines using the write data drivers in response to the gating; and

storing data in a memory cell in response to driving data.

7. The method of claim 6, wherein the recited steps are initiated in the recited order.

8. The method of claim 6, wherein the memory device is a burst extended data out dynamic random access memory device.

9. The method of claim 6, wherein gating the write enable signal through at least one of the data driver enable circuits in response to deasserting the equilibrate signal comprises:

latching the write enable signal;

generating the equilibrate signal based on detection of an address transition; and

logically combining a version of the latched write enable signal and a version of the equilibrate signal.

10. The method of claim 9, wherein logically combining the version of the latched write enable signal and the version of the equilibrate signal comprises nanding the version of the latched write enable signal and the version of the equilibrate signal.

11. The method of claim 9, wherein the memory device includes a sense amplifier and gating occurs in logic circuitry proximate to the sense amplifier.

12. The method of claim 6, wherein providing an address to the memory device comprises providing an address to a memory device including:

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of at least 10 address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter.

13. The method of claim 6, wherein the memory comprises a memory organized according to a pipelined or prefetched architecture.

14. The method of claim 6, wherein the write enable signal is an active-low signal.

15. A method of storing data in a system, comprising:

providing a first address from a microprocessor to a burst access memory organized according to a prefetch architecture and including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first data bit to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

16. The method of claim 15, wherein the write enable signal is an active-low signal.

17. A method of storing data in a system, comprising:

providing a burst access memory organized according to a pipelined architecture and including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first address to the memory from a microprocessor;

providing a first data bit to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

18. The method of claim 17, wherein the write enable signal is an active-low signal.

19. A method of storing data in a system, comprising:

providing a burst access memory including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first address to the memory from a microprocessor;

providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

20. The method of claim 19, wherein providing the second data bit comprises providing a second plurality of data bits, latching the second plurality of data bits with a successive transition of the active-low column address strobe signal, the successive transition immediately succeeding the transition of the column address strobe signal used to latch the first plurality of data bits.

21. The method of claim 19, wherein the write enable signal is an active-low signal.

22. A method of storing data in a system, comprising:

providing a burst access memory including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first address to the memory from a microprocessor;

providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address, wherein advancing the address counter comprises advancing the address counter in response to each transition of a column-address strobe signal;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

23. The method of claim 22, wherein the write enable signal is an active-low signal.

24. A method of storing data in a system, comprising:

providing a first address from a microprocessor to a burst access memory including;

a memory array coupled to a column decoder and a row decoder,

a latch coupled to the row decoder;

an active-low row address strobe input coupled to the latch;

a plurality of address inputs coupled to the latch;

a counter coupled between the plurality of address inputs and the column decoder; and

an active-low column address strobe input coupled to the counter;

providing a first data bit to the memory, wherein providing the first data bit comprises providing a first plurality of data bits, latching the first plurality of data bits with a transition of an active-low column address strobe signal when a first column address for a sequence of column addresses is latched;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first data bit in a memory cell selected by the first address;

advancing an address counter within the memory to provide a second address, wherein advancing the address counter comprises advancing the address counter in response to receiving a plurality of pulses of a column-address strobe signal;

providing a second data bit to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second data bit in a memory cell selected by the second address in response to deasserting the equilibration signal.

25. The method of claim 24, wherein the write enable signal is an active-low signal.

26. A method of storing data in a system, comprising:

providing a first column address from a microprocessor to a burst access memory;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.

27. The method of claim 26, wherein the write enable signal is an active-low signal.

28. A method comprising:

providing a random access memory device having a pinout comprising a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin;

asserting an equilibrate signal to an equilibration device to equilibrate data lines of the memory device;

performing a burst mode access of the memory device; and

latching only one read-write control signal for the burst mode access.

29. The method of claim 28, wherein the recited steps are initiated in the recited order.

30. The method of claim 28, wherein the memory device is a burst extended data out dynamic random access memory device.

31. A method comprising:

providing a memory device having a pinout consisting essentially of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin, wherein the memory device includes two or more output drivers coupled to output data through the data output pins; and

performing a burst mode access of the memory device, wherein performing the burst mode access comprises;

operating the output drivers to drive a byte from memory device onto the data output pins;

continuing operation of the drivers to drive the byte onto the data output pins without tri-stating the data output pins during predetermined intervals of a strobe signal on at least one of the /RAS or the /CAS input pins; and

latching only one read-write control signal for the burst mode access.

32. The method of claim 31, wherein the recited steps are initiated in the recited order.

33. The method of claim 32, wherein the memory device is a burst extended data out dynamic random access memory device.

34. The method of claim 31, wherein performing the burst mode access of the memory device further comprises:

inputting a single address to the memory device;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal, wherein sequentially outputting two or more bytes from the memory device, comprises;

operating two or more output drivers in the memory device to drive a byte from the memory device onto data output pins coupled to the output drivers; and

continuing operation of the drivers to drive the byte onto the data output pins without tri-stating the data output pins during predetermined intervals of a strobe signal on at least one of an /RAS input pin and an /CAS input pin in the memory device.

35. The method of claim 34:

wherein providing the memory device comprises providing a memory organized according to a prefetch architecture and having a memory array; and

wherein performing the burst mode access comprises;

using a least significant bit of a column address to select between odd and even halves of the memory array; and

using other bits of the column address to select a column of the memory array.

36. The method of claim 34:

wherein providing the memory device comprises providing a memory organized according to a prefetch architecture and having a memory array; and

wherein performing the burst mode access comprises advancing a column address once for every two active transitions of a strobe signal on the /CAS input pin.

37. The method of claim 34:

wherein providing the memory device comprises providing a memory organized according to a pipelined architecture having a pipeline length; and

wherein performing the burst mode access comprises outputting data from the memory device, with the data being temporally offset during output by a number of cycles equal to the pipeline length or a desired latency relative to a strobe signal on the /CAS input pin.

38. The method of claim 31 wherein performing the burst mode access of the memory device comprises providing a first plurality of data bits, and latching the first plurality of data bits with a transition of an active-low signal on the /CAS input pin when a first column address for a sequence of column addresses is latched.

39. The method of claim 38, wherein providing the second data bit comprises providing a second plurality of data bits, and latching the second plurality of data bits with a successive transition of the active-low strobe signal on the /CAS input pin, the successive transition immediately succeeding the transition of a signal used to latch the first plurality of data bits.

40. The method of claim 31, wherein the write enable signal is an active-low signal.

41. The method of claim 31, wherein performing a burst mode access of the memory device comprises:

providing a first column address to the memory from a microprocessor;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.

42. The method of claim 41, wherein disabling the data driver enable circuits in response to asserting the equilibration signal comprises gating a version of the write enable signal with the equilibration signal.

43. The method of claim 41, wherein the recited steps are initiated in the recited order.

44. A method comprising:

performing a burst mode access of a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin; and

latching only one read-write control signal for the burst mode access.

45. The method of claim 44, wherein the recited steps are initiated in the recited order.

46. The method of claim 44, wherein the memory device is a burst extended data out dynamic random access memory device.

47. A method comprising:

providing a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin;

initiating a burst mode access of the memory device; and

responding to signal transitions occurring only at the /CAS input pin during the burst mode access.

48. The method of claim 47, wherein the recited steps are initiated in the recited order.

49. The method of claim 47, wherein the memory device is a burst extended data out dynamic random access memory device.

50. The method of claim 47, wherein performing a burst mode access of the memory device comprises:

providing a first column address to the memory from a microprocessor;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.

51. A method comprising:

initiating a burst mode access of a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin; and

during the burst mode access, generating memory addresses within the memory device in response to corresponding signal transitions at the /CAS input pin.

52. The method of claim 51, wherein the burst mode access comprises a burst read cycle.

53. The method of claim 51, wherein generating memory addresses within the memory devices occurs in response to falling edge signal transitions at the /CAS input pin.

54. The method of claim 51, wherein performing a burst mode access of the memory device comprises:

providing a first column address to the memory from a microprocessor;

providing a first plurality of data bits to the memory;

asserting a write enable signal to a distributed plurality of data driver enable circuits within the memory and located in close proximity to write data drivers;

storing the first plurality of data bits in a portion of the memory dependent on the first column address;

automatically providing a second column address to the memory that is not provided by the microprocessor without the requirement of advancing an address counter within the memory to provide a second address;

providing a second plurality of data bits to the memory;

asserting an equilibration signal within the memory while maintaining the write enable signal to the plurality of data driver enable circuits;

disabling the data driver enable circuits in response to asserting the equilibration signal;

deasserting the equilibration signal; and

storing the second plurality of data bit in another portion of the memory dependent on the second column address, in response to deasserting the equilibration signal.