Non-volatile semiconductor memory device and electric device with the same

• US 20050036395A1
• Filed: 07/16/2004
• Published: 02/17/2005
• Est. Priority Date: 07/29/2003
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hara, Takahiko, Maejima, Hiroshi
• Granted Patent: US 7,050,346 B2
• Time in Patent Office: Days
• US Class Current: 365/232
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A non-volatile semiconductor memory device includes a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read and write data in association with the cell array, wherein the sense amplifier circuit includes: differential amplifier having first and second input nodes and configured to amplify a difference voltage between the first and second input nodes; a data transfer circuit configured to selectively connect the first input node to a bit line in the cell array; a reference voltage setting circuit configured to apply a reference voltage to the second input node of the differential amplifier; and a data storing circuit configured to temporarily hold a loaded write data at the first input node of the differential amplifier, and control the reference voltage at the second input node of the differential amplifier in correspondence with the write data held therein.

Claims

1. A non-volatile semiconductor memory device comprising a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read and write data in association with said cell array, wherein

said sense amplifier circuit comprises:

a differential amplifier having first and second input nodes and configured to amplify a difference voltage between said first and second input nodes;

a data transfer circuit configured to selectively connect said first input node to a bit line of said cell array;

a reference voltage setting circuit configured to apply a reference voltage to said second input node of said differential amplifier; and

a data storing circuit configured to temporarily hold a loaded write data at said first input node of said differential amplifier, and control the reference voltage at said second input node of said differential amplifier in correspondence with the write data held therein.

2. The non-volatile semiconductor memory device according to claim 1, wherein

said data transfer circuit comprises:

a clamping transistor disposed between a bit line of said cell array and a sense node for clamping a bit line voltage and serving as a pre-sense amplifier;

a precharging transistor connected to said sense node for precharging said sense node and bit line;

a transfer NMOS transistor disposed between said sense node and said first input node of said differential amplifier, and selectively driven to turn on in a data write mode; and

a transfer PMOS transistor disposed between said sense node and said first input node of said differential amplifier, and selectively driven to turn on in a data read mode.

3. The non-volatile semiconductor memory device according to claim 1, wherein

in a verify-read operation in a data write cycle, the write data held at said first input node of said differential amplifier is transferred to said data storing circuit before bit line data is transferred to said differential amplifier.

4. The non-volatile semiconductor memory device according to claim 1, wherein

in a verify-read operation in a data write cycle, said differential amplifier is disabled after said write data held at said first input node has been transferred to said data storing circuit and before bit line data is transferred to said differential amplifier, and then the reference voltage is set at said second input node by said reference voltage setting circuit, successively the reference voltage of said second node is adjusted based on the write data held in said data storing circuit.

5. The non-volatile semiconductor memory device according to claim 4, wherein

the write data held at said first input node of said differential amplifier is a “

L”

level of “

0”

data or a “

H”

level of “

1”

data, and wherein

the reference voltage initially applied to said second input node of said differential amplifier is VREF as being an intermediate value between the “

H” and

“

L”

levels, and wherein

said data storing circuit controls said second input node in such a manner that the reference voltage VREF is maintained in case the write data is “

0”

, while it is reduced to ground potential Vss from VREF in case the write data is “

1”

.

6. The non-volatile semiconductor memory device according to claim 4, wherein

the threshold voltage Vtp of said transfer PMOS transistor and the reference voltage VREF are selected as satisfying a relationship of Vss<

|Vtp|<

VREF, and wherein

said differential amplifier is activated in a verify-read operation after data writing to operate in such a manner that said first input node changes to have a “

H”

level in case write data “

0”

is sufficiently written or write data is “

1”

, while said first input node changes to have a “

L”

level in case write data “

0”

is insufficiently written.

7. The non-volatile semiconductor memory device according to claim 5, wherein

said data storing circuit comprises:

a first NMOS transistor with a gate serving as a data storing node and a source to which ground potential Vss is applied;

a second NMOS transistor, whose gate is driven by a first timing signal, disposed between said first input node of said differential amplifier and the gate of said first NMOS transistor for transferring the write data held at said first input node to the gate of said first NMOS transistor; and

a third NMOS transistor, whose gate is driven by a second timing signal, disposed between a drain of said first NMOS transistor and said second input node of said differential amplifier for transferring ground potential Vss to said second input node of said differential amplifier in case write data is “

1”

.

8. The non-volatile semiconductor memory device according to claim 1, further comprising a judgment circuit configured to monitor the level of said second input node of said differential amplifier, and judge a data write completion in a data write cycle.

9. The non-volatile semiconductor memory device according to claim 1, wherein

said cell array comprises a plurality of NAND cell units each having plural memory cells connected in series, control gates of which are connected to different word lines respectively, one end of each NAND cell unit being connected to a bit line via a first select transistor, the other end to a source line via a second select transistor.

10. An electric card equipped with a non-volatile semiconductor memory device, said device comprising a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read and write data in association with said cell array, wherein said sense amplifier circuit comprises:

a differential amplifier having first and second input nodes and configured to amplify a difference voltage between said first and second input nodes;

a data transfer circuit configured to selectively connect said first input node to a bit line of said cell array;

a reference voltage setting circuit configured to apply a reference voltage to said second input node of said differential amplifier; and

a data storing circuit configured to temporarily hold a loaded write data at said first input node of said differential amplifier, and control the reference voltage at said second input node of said differential amplifier in correspondence with the write data held therein.

11. An electric device comprising:

a card interface;

a card slot connected to said card interface; and

an electric card defined in claim 10 and electrically connectable to said card slot.

12. The electric device according to claim 11, wherein

said electric device is a digital still camera.

13. A non-volatile semiconductor memory device comprising a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read data in association with said cell array, wherein

said sense amplifier circuit comprises:

a differential amplifier having first and second input nodes and configured to amplify a difference voltage between said first and second input nodes;

a data transfer circuit configured to selectively connect said first input node to a bit line of said cell array; and

a reference voltage setting circuit configured to apply a reference voltage, which serves for determining the bit line data transferred to said first input node, to said second input node of said differential amplifier, said reference voltage being generated based on charge-sharing between said second input node of said differential amplifier and a reference node selectively connected to said second input node, and wherein

said data transfer circuit comprises;

a clamping transistor disposed between a bit line of said cell array and a sense node for clamping a bit line voltage and serving as a pre-sense amplifier;

a first precharging transistor connected to said sense node for precharging said sense node and bit line;

a transferring transistor disposed between said sense node and said first input node of said differential amplifier; and

a second precharging transistor connected to said first input node of said differential amplifier for precharging said first input node.

14. The non-volatile semiconductor memory device according to claim 13, wherein

said reference voltage setting circuit comprises:

a third precharging transistor connected to said second input node of said differential amplifier for precharging it at a first voltage;

a fourth precharging transistor connected to said reference node for precharging it at a second voltage lower than said first voltage;

a first and second capacitor connected to said second input node and said reference node for charge-storing; and

an equalizing transistor disposed between said second input node and said reference node for selectively equalizing these nodes so as to generate the reference voltage based on charge-sharing between said third and fourth capacitors.

15. The non-volatile semiconductor memory device according to claim 13, wherein

said cell array comprises a plurality of NAND cell units each having plural memory cells connected in series, control gates of which are connected to different word lines respectively, one end of each NAND cell unit being connected to a bit line via a first select transistor, the other end connected to a source line via a second select transistor.

18. The electric device according to claim 13, wherein said electric device is a digital still camera.

16. An electric card equipped with a non-volatile semiconductor memory device, said device comprising a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read data in communication with said cell array, wherein

said sense amplifier circuit comprises:

a differential amplifier having first and second input nodes and configured to amplify a difference voltage between said first and second input nodes;

a data transfer circuit configured to selectively connect said first input node to a bit line of said cell array; and

a reference voltage setting circuit configured to apply a reference voltage, which serves for determining the bit line data transferred to said first input node, to said second input node of said differential amplifier, said reference voltage being generated based on charge-sharing between said second input node of said differential amplifier and a reference node selectively connected to said second input node, and wherein

said data transfer circuit comprises;

a clamping transistor disposed between a bit line of said cell array and a sense node for clamping a bit line voltage and serving as a pre-sense amplifier;

a first precharging transistor connected to said sense node for precharging said sense node and bit line;

a transferring transistor disposed between said sense node and said first input node of said differential amplifier; and

a second precharging transistor connected to said first input node of said differential amplifier for precharging said first input node.

17. An electric device comprising:

a card interface;

a card slot connected to said card interface; and

an electric card defined in claim 16 and electrically connectable to said card slot.