Systems for synchronizing resets in multi-clock frequency applications

• US 20050036577A1
• Filed: 08/14/2003
• Published: 02/17/2005
• Est. Priority Date: 08/14/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Sweet, James D.
• Granted Patent: US 7,260,166 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/035 Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

Abstract

Methods and systems for synchronizing a reset signal with a local clock that drives a circuit. In the circuit, the reset signal can be used to reset one or more flip-flops, memory devices, and/or logic. Sychronization of the reset signal allows the reset signal to change at an appropriate time period in relation to the lock clock signal driving the circuit. This ensures the circuit will remain stable during reset, and no data will be lost as it is processed in the circuit. Other aspects of the invention can include using a plurality of reset signals (e.g., software, hardware, local software, etc.) to form the reset signal and using a reset control system to control resets during testing of the circuit.

Claims

1. A system for synchronizing a reset signal to a local clock, comprising:

a local clock terminal;

a reset terminal;

a synchronized reset output terminal; and

synchronizing circuitry coupled between the clock terminal, the reset terminal, and the synchronized reset output terminal;

wherein the synchronizing circuitry synchronizes a received reset signal to the local clock signal and outputs a synchronized reset signal on the synchronized reset output terminal.

2. The system according to claim 1, wherein the synchronizing circuitry comprises:

a first flip-flop including;

a clock input coupled to the clock terminal,

a reset input coupled to the reset terminal, and

a data input coupled to a pull up; and

a second flip-flop including;

a clock input coupled to the clock terminal,

a reset input coupled to the reset terminal,

a data input coupled to a data output of the first flip-flop, and

a data output coupled to the synchronized reset output terminal.

3. The system according to claim 2, further comprising a reset generator coupled to the reset terminal.

4. The system according to claim 3, wherein the reset generator is driven using a second clock.

5. The system according to claim 3, wherein the reset generator comprises:

a hardware reset device outputting a hardware reset signal;

a software reset device outputting a software reset signal; and

a logic gate that receives the hardware and software reset signals and generates an output reset signal received at the reset terminal of the first and second flip-flops.

6. The system of claim 5, wherein the software reset device comprises a synchronous reset terminal that receives the hardware reset signal.

7. The system according to claim 3, wherein the reset generator comprises:

a software reset device outputting a software reset signal;

a local software reset device outputting a local software reset signal;

a first logic gate receiving the software reset signal and the local software reset signal and generating a output software reset signal;

a hardware reset device outputting a hardware reset signal; and

a second logic gate that receives the hardware and output software reset signals and generates an output reset signal received at the reset terminal of the first and second flip-flops.

8. The system of claim 7, wherein the software reset device comprises a synchronous reset terminal that receives the hardware reset signal.

9. The system according to claim 3, further comprising test control circuitry coupled to the reset generator and the synchronizing circuitry, the test control circuitry comprising:

a first multiplexer that receives a reset output signal from the reset generator at a first input and a hardware reset signal at a second input;

a second multiplexer that receives the synchronized reset signal at a first input and the hardware reset signal at a second input; and

a controller coupled to control terminals of the first and second multiplexers to selectively control the multiplexers.

10. The system of claim 9, wherein the first and second multiplexers output the hardware reset signal during a test mode.

11. The system of claim 10, wherein the test mode comprises a scan test mode.

12. A system comprising:

means for processing data; and

means for synchronizing a reset with of the means for processing data.

13. The system of claim 12, further comprising:

means for performing a scanning test of the means for processing data.

14. The system of claim 12, further comprising a means for generating the reset signal.

15. The system of claim 14, wherein the means for generating a reset signal comprises:

means for generating a reset output signal from a hardware reset signal and a software reset signal.

16. The system of claim 14, wherein the means for generating a reset signal comprises:

means for generating a reset output signal from a hardware reset signal, a software reset signal, and a local software reset signal.