Random noise generator and a method for generating random noise

• US 20050038840A1
• Filed: 09/21/2004
• Published: 02/17/2005
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Miller, Robert H. Jr.
• Granted Patent: US 7,401,108 B2
• Time in Patent Office: Days
• US Class Current: 708/250
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H04L 9/001 using chaotic signals

Abstract

A random noise signal generator circuit comprising a random noise source that produces a random noise signal, an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal, a feedback loop having a DC offset correction circuit, and a summer. The DC offset correction circuit processes a fed back portion of the amplified random noise signal to produce a DC offset correction signal. The summer sums the random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal. The summer is electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry. The amplification circuitry amplifies the summed signal to produce a random noise output signal.

Claims

1. A random noise signal generator circuit comprising:

a random noise source that produces a random noise signal;

an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal;

a feedback loop having a DC offset correction circuit, the feedback loop passing a fed back portion of the amplified random noise signal through the DC offset correction circuit to produce a DC offset correction signal; and

a summer that sums a random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal, the summer being electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry, the amplification circuitry amplifying the summed signal to produce a random noise output signal.

2. The random noise signal generator circuit of claim 1, wherein the random noise source is a thermal noise source.

3. The random noise signal generator circuit of claim 1, wherein the DC offset correction circuit is a lowpass filter circuit.

4. The random noise signal generator circuit of claim 1, wherein the DC offset correction circuit is an automatic gain control (AGC) circuit.

5. The random noise signal generator circuit of claim 1, wherein the amplification circuitry includes at least a first gain stage and a second gain stage, the second gain stage having a higher gain than the first gain stage, the first gain stage corresponding to an input stage of the amplification circuitry.

6. The random noise signal generator circuit of claim 1, wherein the amplification circuitry includes at least a first gain stage, a second gain stage and a third gain stage, the second gain stage having a higher gain than the first gain stage, the third gain stage having a higher gain than the second gain stage, the first gain stage corresponding to an input stage of the amplification circuitry.

7. The random noise signal generator circuit of claim 1, wherein the summer includes a capacitor electrically coupled to the random noise source and a transistor electrically coupled to the DC offset correction circuit, the transistor functioning as a resistor, the transistor and capacitor being electrically coupled to each other and to an input of the amplification circuitry.

8. The random noise signal generator circuit of claim 1, wherein the DC offset correction circuit is a lowpass filter circuit that includes transistors connected to operate as a capacitor and transistors connected to operate as a resistor to form a resistor-capacitor (RC) circuit.

9. A method for generating a random noise signal, the method comprising:

generating a random noise signal with a random noise source;

amplifying the random noise signal to produce an amplified random noise signal;

processing a fed back portion of the amplified random noise signal by a DC offset correction circuit to produce a DC offset correction signal;

summing a random noise signal generated by the random noise source with the DC offset correction signal to produce a summed signal; and

amplifying the summed signal to produce a random noise output signal.

10. The method of claim 9, wherein the random noise source is a thermal noise source.

11. The method of claim 9, wherein the DC offset correction circuit is a lowpass filter circuit and wherein the DC offset correction signal is a lowpass filtered signal.

12. The method of claim 9, wherein the step of amplifying the random noise signal includes inputting the random noise signal to amplification circuitry that includes at least a first gain stage and a second gain stage, the second gain stage having a higher gain than the first gain stage, the first gain stage corresponding to an input stage of the amplification circuitry.

13. The method of claim 9, wherein the step of amplifying the random noise signal includes inputting the random noise signal to amplification circuitry that includes at least a first gain stage, a second gain stage and a third gain stage, the second gain stage having a higher gain than the first gain stage, the third gain stage having a higher gain than the second gain stage, the first gain stage corresponding to an input stage of the amplification circuitry.

14. The method of claim 9, wherein the summing step includes summing the signals with a summer that includes a capacitor electrically coupled to the random noise source and a transistor electrically coupled to the DC offset correction circuit, the transistor functioning as a resistor, the capacitor and transistor being electrically coupled to each other to form a summing node at an input to the amplification circuitry.

15. A method for generating a series of random bits, the method comprising:

generating a first random noise signal with a first random noise source;

generating a second random noise signal with a second random noise source;

amplifying the first random noise signal in first amplification circuitry to produce a first amplified random noise signal;

amplifying the second random noise signal in second amplification circuitry to produce a second amplified random noise signal;

processing a fed back portion of the first amplified random noise signal by a first DC offset correction circuit to produce a first DC offset correction signal;

processing a fed back portion of the second amplified random noise signal by a second DC offset correction circuit to produce a second DC offset correction signal;

summing a random noise signal generated by the first random noise source with the first DC offset correction signal to produce a first summed signal;

summing a random noise signal generated by the second random noise source with the second DC offset correction signal to produce a second summed signal;

amplifying the first summed signal to produce a first random noise output signal;

amplifying the second summed signal to produce a second random noise output signal; and

comparing the first random noise output signal with the second random noise output signal and producing a digital 1 or a digital 0 depending on results of the comparison.

16. The method of claim 15, wherein the first and second random noise sources are thermal noise sources.

17. The method of claim 15, wherein the first and second DC offset correction circuits are lowpass filter circuits.

18. The method of claim 15, wherein the first and second DC offset correction circuits are automatic gain control circuits.