Method and apparatus for accessing a memory

• US 20050038941A1
• Filed: 08/14/2003
• Published: 02/17/2005
• Est. Priority Date: 08/14/2003
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Culley, Paul R., Hilland, Jeffrey R., Wendt, James G., Barron, Dwight L., Chadalapaka, Mallikarjun
• Granted Patent: US 7,617,376 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/4009 with data restructuring
• CPC Class Codes: H04L 67/00 Network arrangements or protocols for supporting network services or applications user-to-user messaging H04L51/00; network arrangements, protocols or services for supporting real-time applications in data packet communications networks H04L65/00

Abstract

The disclosed embodiments relate to an optimized memory registration mechanism that may comprise an upper layer protocol that associates I/O buffers with memory regions and that manages steering tags. The memory regions may be associated with a translation page table. The upper layer protocol may allocate one of the steering tags associated with at least one of the memory regions for a memory operation.

Claims

1. A memory access mechanism, comprising:

an upper layer protocol

a translation page table for storing data corresponding to a plurality of memory regions; and

a plurality of steering tags that are controlled by the upper layer protocol, the upper layer protocol allocating at least one of the plurality of steering tags to be associated with at least one of the plurality of memory regions for a memory operation.

2. The memory access mechanism set forth in claim 1, wherein the steering tags are allocated by execution of a verb.

3. The memory access mechanism set forth in claim 2, wherein the verb is executed at initialization.

4. The memory access mechanism set forth in claim 2, wherein the verb is executed after initialization.

5. The memory access mechanism set forth in claim 1, wherein the at least one of the plurality of steering tags is associated with an entry in the translation page table that is associated with the at least one of the plurality of memory regions.

6. The memory access mechanism set forth in claim 5, wherein the entry of the translation page table accesses a physical address table to access the at least one of the plurality of memory regions for the memory operation.

7. The memory access mechanism set forth in claim 1, wherein the translation page table uses a tagged offset in a request generated by the upper layer protocol to access the at least one of the plurality of memory regions for the memory operation.

8. A computer network, comprising:

a first computer system having a first consumer and at least one input/output device;

a second computer system having a second consumer and at least one input/output device;

a switch network that connects the first and second computer systems for communication; and

wherein the at least one input/output device in the first computer system comprises a memory access mechanism, the memory access mechanism comprising;

a plurality of buffers associated with the consumer; and

a plurality of steering tags that are managed by the consumer, wherein the consumer allocates one of the plurality of steering tags to be associated with at least one of the plurality of buffers for a memory access operation.

9. The computer network set forth in claim 8, wherein the first computer system generates a request for the memory access operation to be transmitted to the second computer system.

10. The computer network set forth in claim 9, wherein the request comprises the one of the plurality of steering tags.

11. The computer network set forth in claim 9, wherein the request comprises an indicator that permits a physical steering tag mode.

12. The computer network set forth in claim 8, wherein the consumer invalidates the one of the plurality of steering tags once the memory access operation is completed.

13. The computer network set forth in claim 8, wherein the memory access operation is a remote direct memory access write operation.

14. The computer network set forth in claim 8, wherein the memory access operation is a remote direct memory access read operation.

15. A method for providing access to a memory, the method comprising the acts of:

allocating a plurality of steering tags associated with an upper layer protocol in a first node;

allocating a plurality of buffers associated with the upper layer protocol;

issuing a command to a “

remote direct memory access”

network interface card after the allocation of the plurality of steering tags has been completed;

binding one of the plurality of steering tags to at least one of the plurality of buffers once a command is received at the upper layer protocol which accomplishes the binding by issuing a request to the “

remote direct memory access”

network interface card.

16. The method set forth in claim 15, comprising communicating the one of the plurality of steering tags to a second node.

17. The method set forth in claim 15, comprising performing the command to access at least one of the plurality of buffers once the command is received at the “

remote direct memory access”

network interface card.

18. The method set forth in claim 15, wherein the allocation of the plurality of steering tags occurs at an initialization of the first node.

19. The method set forth in claim 15, comprising issuing a verb to perform the allocation of the plurality of steering tags.

20. The method set forth in claim 15, comprising deallocating the plurality of steering tags associated with the upper layer protocol in the first node.