Data converter with statistical domain output

• US 20050038942A1
• Filed: 06/15/2004
• Published: 02/17/2005
• Est. Priority Date: 08/17/1999
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Eric Swanson
• Inventors: Swanson, Eric
• Granted Patent: US 6,931,513 B2
• Time in Patent Office: Days
• US Class Current: 710/72
• CPC Class Codes: G01R 23/167 with digital filters

Abstract

An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting received input data from the first domain to a second domain different from the first domain. A statistical processor is provided for obtaining statistical information from the output of the data converter and processing the obtained statistical information in accordance with a predetermined processing algorithm. An output on the integrated circuit allow access of the processed statistical information by the statistical processor external to the integrated circuit.

Claims

1. A method for collecting statistics in an integrated circuit on data, comprising the steps of:

receiving on an input input data in a first data domain;

converting received input data with a data converter from the first data domain to a second data domain different from the first data domain;

determining with a statistical processor statistical information from the finite collected data from the output of the data converter in the second data domain the step of determining with the statistical processor providing processed statistical output information in the second data domain;

wherein the step of determining operates on a finite amount of collected data from the step of converting;

determining when the completion of the statistical information has occurred; and

allowing access external to the integrated circuit through an output interface on the integrated circuit to the output of the statistical processor only after the completion of the statistical information.

2. The method of claim 1, wherein the step of converting operates in a time domain.

4. The method of claim 1, wherein the step of converting with the data converter operates in the time domain and further comprising the step of receiving the converted data in the second domain from the data converter in the time domain with a time domain/frequency domain converter and converting the received data to frequency domain data in accordance with a predetermined frequency domain conversion algorithm and wherein the step of determining with the statistical processor is operable to obtain statistical information from the output of the time domain/frequency domain converter for processing thereof.

5. The method of claim 4 and further comprising multiplexing with a multiplexer the operation of the step of determining with the statistical processor to select either the output of the data converter or the output of the time domain/frequency domain converter.

6. The method of claim 1 and further comprising storing in memory at least a portion of the processed obtained statistical information.

7. The method of claim 1, wherein:

the step of converting with the data converter is operable to convert the received input data in the first domain to a second domain at a first data width to provide a first amount of data; and

the step of determining with the statistical processor is operable to generate a second and lesser amount of data than the output of the data converter as a result of processing thereby of the obtained statistical information.

8. The method of claim 1, wherein the first domain is an analog data domain and the second domain is a digital data domain.

9. The method of claim 8, wherein the step of converting with the data converter has an output in the digital domain of a first data width and an associated data transfer rate and the output interface has a second data width less than the first data width.

10. The method of claim 9, wherein the step of interfacing provides a serial output interface.

11. The method of claim 1 and further comprising the steps of:

providing a dedicated output indicative of information regarding the processing by the step of determining with the statistical processor; and

step of determining with the statistical processor operable to generate an indication for output on the dedicated output.

12. The method of claim 1, wherein the step of converting with the data converter provides samples at a predetermined sample rate and the step of determining with the statistical processor operates on a dataset of the samples as the obtained statistical information.

13. The method of claim 12, wherein the samples in the dataset are adjacent and consecutive.

14. The method of claim 12, wherein the samples in the dataset are quasi-periodic.

15. The method of claim 1, wherein the step of determining with the statistical processor is further operable to process the obtained statistical information in accordance with a predetermined processing algorithm to provide processed statistical information.

16. The method of claim 15, wherein the step of determining with the statistical processor is operable to process the obtained statistical information to determine if the underlying data has an unnatural pattern associated therewith.

17. The method of claim 16, wherein the step of interfacing includes the step of outputting a signal indicative of the presence of an unnatural pattern.

21. The method of claim 1, wherein the step of converting with the data converter operates in the time domain and further comprising the step of processing with a post processor to further process the output of the data converter in accordance to a predetermined processing algorithm.

22. The method of claim 21, and further comprising for multiplexing with a multiplexer the operation of the statistical processor to select either the output of the data converter or the output of the post processor.

23. The method of claim 1, wherein the step of determining with the statistical processor includes the step of determining the completion of a statistical operation and the output interface is operable to provide as an output an indication of such completion.

24. The method of claim 23, wherein the step of interfacing is operable to output data and the indication is embedded within the output data as an addendum thereto.

25. The method of claim 23, wherein the completion of the statistical operation comprises determining the presence of an unnatural pattern.

26. The method of claim 1, wherein the step of interfacing allows external access to the output of the data converter.

3. (Cancelled).

18-20. -20. (Cancelled).

27. An integrated circuit, comprising:

an input for receiving input data in a first data domain;

a data converter for converting received input data from said first data domain to a second domain different from said first domain said data converter collecting data in finite amounts;

a statistical processor for determining statistical information from the output of said data converter, said statistical processor operating on said fixed amounts of data to provide a statistical result on each of said fixed amounts of data, the statistical processor providing processed statistical output information in said second data domain; and

an output interface for allowing external access to the output of said statistical processor at the completion of processing of a given one of said fixed amounts of data.

28. The integrated circuit of claim 27, wherein said data converter operates in a time domain.

30. The integrated circuit of claim 27, wherein said data converter operates in the time domain and further comprising a time domain/frequency domain converter that is operable to receive the converted data in said second domain from said data converter in the time domain and convert the received data to frequency domain data in accordance with a predetermined frequency domain conversion algorithm and wherein said statistical processor is operable to obtain statistical information from the output of said time domain/frequency domain converter for processing thereof.

31. The integrated circuit of claim 30 and further comprising a multiplexer for multiplexing the operation of said statistical processor to select either the output of said data converter or the output of said time domain/frequency domain converter.

32. The integrated circuit of claim 27 and further comprising a memory for storing at least a portion of the processed obtained statistical information.

33. The integrated circuit of claim 27, wherein:

said data converter is operable to convert the received input data in said first domain to a second domain at a first data width to provide a first amount of data; and

said statistical processor is operable to generate a second and lesser amount of data than the output of said data converter as a result of processing thereby of said obtained statistical information.

34. The integrated circuit of claim 27, wherein said first domain is an analog data domain and said second domain is a digital data domain.

35. The integrated circuit of claim 34, wherein said data converter has an output in the digital domain of a first data width and an associated data transfer rate and said output interface has a second data width less than said first data width.

36. The integrated circuit of claim 35, wherein said output interface provides a serial output interface.

37. The integrated circuit of claim 27 and further comprising:

a dedicated output indicative of information regarding the processing by said statistical processor; and

said statistical processor operable to generate an indication for output on said dedicated output.

38. The integrated circuit of claim 27, wherein said data converter provides samples at a predetermined sample rate and said statistical processor operates on a dataset of said samples as said obtained statistical information.

39. The integrated circuit of claim 38, wherein said samples in said dataset are adjacent and consecutive.

40. The integrated circuit of claim 38, wherein said samples in said dataset are quasi-periodic.

41. The integrated circuit of claim 27, wherein said statistical processor is further operable to process said obtained statistical information in accordance with a predetermined processing algorithm to provide processed statistical information.

42. The integrated circuit of claim 41, wherein said statistical processor is operable to process said obtained statistical information to determine if the underlying data has an unnatural pattern associated therewith.

43. The integrated circuit of claim 42, wherein said output interface includes means for outputting a signal indicative of the presence of an unnatural pattern.

47. The method of claim 27, wherein said data converter operates in the time domain and further comprising a post processor for further processing the output of said data converter in accordance to a predetermined processing algorithm.

48. The method of claim 47, and further comprising a multiplexer for multiplexing the operation of said statistical processor to select either the output of said data converter or the output of said post processor.

49. The method of claim 27, wherein said statistical processor includes means for determining the completion of a statistical operation and said output interface is operable to provide as an output an indication of such completion.

50. The method of claim 49, wherein said output interface is operable to output data and said indication is embedded within said output data as an addendum thereto.

51. The method of claim 50, wherein said completion of said statistical operation comprises determining the presence of an unnatural pattern.

52. The method of claim 27, wherein said output interface allows external access to the output of said data converter.

29. (Cancelled).

44-46. -46. (Cancelled).