Interference signal decoupling on a printed circuit board

• US 20050039935A1
• Filed: 09/29/2003
• Published: 02/24/2005
• Est. Priority Date: 02/19/2002
• Status: Active Grant

• Current Assignee: Lowell E. Kolb, Samuel M. Babb
• Original Assignee: Lowell E. Kolb, Samuel M. Babb
• Inventors: Babb, Samuel M., Kolb, Lowell E.
• Granted Patent: US 7,109,817 B2
• Time in Patent Office: Days
• US Class Current: 174/350
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 3/284 for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 9/0024 Shield cases mounted on a PCB, e.g. cans or caps or conformal shields

Abstract

A decoupling circuit on a printed circuit board is disclosed. The decoupling circuit comprises an electrical filter circuit electrically connected between an interconnect post and a ground land of the printed circuit board. The ground land is connected to a ground plane in the printed circuit board. The electrical filter shunts conducted interfering signals received at the interconnect post to the ground plane. Components of the electrical filter circuit and ground plane form a first receiver loop in which induced interfering signals can be generated. The decoupling circuit also comprises a second receiver loop comprising a conductive coating of an EMI shield conformingly adhered to surfaces of the decoupling circuit, and a conductive path of the first receiver loop. The second receiver loop is adapted to have induced therein a signal having a direction and magnitude sufficient to cancel interfering signals induced in the first receiver loop.

Claims

1-24. -24. (Canceled)

25. A circuit board having a signal interconnect post, comprising:

a filter receiver loop in which interfering signals can be induced and comprising an electrical filter circuit connected to the post to filter conducted interfering signals traveling through the post; and

a suppressor receiver loop in which noise suppression signals can be induced, wherein the receiver loops are oriented such that the respective,interfering and noise suppression signals are induced by a same external field and travel in opposite directions through a shared conductive path.

26. The circuit board of claim 25, wherein the filter receiver loop comprises:

a conductor electrically coupled to the post and the electrical filter circuit;

a circuit board ground plane; and

wherein the shared conductive path is a path through the conductor.

27. The circuit board of claim 26, wherein the filter receiver loop further comprises:

a circuit board ground plane; and

a ground via electrically coupled to the conductor and the circuit board ground plane.

28. The circuit board of claim 26, wherein the suppressor receiver loop comprises:

the conductor; and

a conductive coating conformingly adhered to surfaces of the electrical filter circuit.

29. The circuit board of claim 25, wherein the interconnect post comprises one of the group consisting of a signal connector, a power connector and a power post.

30. The noise suppressor of claim 25, wherein the external field is electrostatically, magnetically or electromagnetically coupled with the receiver loops.

31. The noise suppressor of claim 25,

wherein the conductor comprises a surface trace, and

wherein the electrical filter connector is a surface mount capacitor.

32. The noise suppressor of claim 25, wherein the electrical filter circuit comprises:

one or more lumped, distributed or dissipative elements having a frequency characteristic suitable for decoupling the conducted interfering signal from a transmitted signal.

33. The noise suppressor of claim 25, wherein the circuit board further comprises a destination circuit electrically coupled to the post, and wherein the noise suppression signals substantially prevent interfering signals induced in the filter receiver loop from reaching the destination circuit.

34. The noise suppressor of claim 25, wherein the interconnect post receives power from an external power source and wherein the electrical filter circuit decouples high frequency conducted interfering signals from the received power signals.

35. The noise suppressor of claim 25, wherein the conductive coating is part of a EMI shield also comprising a dielectric coating interposed between selected portions of the circuit board and the conductive coating.

36. The noise suppressor of claim 25, wherein the configuration of electrical filter circuit and the arrangement of the selected elements of circuit board are determine so as to minimize the field coupling characteristics of the receiver loop.

37. The noise suppressor of claim 33, wherein the surface mount capacitor is located immediately adjacent to interconnect post.

38. The noise suppressor of claim 33, wherein the ground via is located immediately adjacent to the ground terminal of the capacitor.

39. The noise suppressor of claim 36, wherein the area encompassed by the filter receiver loop is determined to minimize the potential coupling of the filter receiver loop with the external field.

40. The noise suppressor of claim 25, wherein the electrical filter circuit comprises one or more capacitors selected to provide a desired capacitance while minimizing parasitic inductance in the electrical filter circuit.

41. The noise suppressor of claim 25, wherein the filter receiver loop and the noise suppressor loop are constructed and arranged such that an external field electrostatically, magnetically and/or electromagnetically coupled to the filter receiver loop will also be similarly coupled to the noise suppressor loop.

44. The decoupling circuit of claim 41, wherein the electrical filter circuit comprises one or more lumped, distributed or dissipative elements having a frequency characteristic providing a predetermined signal filtering capability.

42. A decoupling circuit on a printed circuit board, comprising:

a first receiver loop comprising an electrical filter circuit electrically connected via a conductive path to an interconnect post and a ground via coupled to a ground plane, the filter configured to shunt to the ground plane conducted interfering signals on the conductor; and

a second receiver loop, comprising a conductive coating adhered to surfaces of the decoupling circuit, and the conductive path, adapted to have induced therein a signal having a direction and magnitude sufficient to cancel at least a portion of interfering signals induced in the first receiver loop.

43. The decoupling circuit of claim 42, wherein the conductive coating is conformally secured to exterior surfaces of the electrical filter circuit and insulated from the electrical filter, interconnect post and conductive path.

45. The decoupling circuit of claim 42, wherein the first and second receiver loops are constructed and arranged to minimize respective field coupling characteristics.

46. The decoupling circuit of claim 42, wherein the electrical filter circuit comprises:

a surface-mounted capacitor mounted immediately adjacent to the interconnect post and connected electrically between the interconnect post and ground via, wherein the ground via is located immediately adjacent to the surface-mounted capacitor.

47. The decoupling circuit of claim 42, further comprising:

a plurality of ground lands located immediately adjacent to and radially-spaced around the electrical filter components, wherein the conductive coating is electrically connected to the ground lands, and wherein the conductive coating, ground plane and ground lands together form a grounded compartment around the electrical filter.

48. The decoupling circuit of claim 42, wherein the receiver loops are oriented such that the respective interfering and noise suppression signals are induced by a same external field and travel in opposite directions through the conductive path.

49. The decoupling circuit of claim 42, wherein the interconnect post comprises one of the group consisting of a signal connector, a power connector and a power post.

50. The decoupling circuit of claim 42, wherein the interconnect post comprises one of the group consisting of a signal connector, a power connector and a power post.

51. The decoupling circuit of claim 48, wherein the external field is electrostatically, magnetically or electromagnetically coupled with the receiver loops.

52. The decoupling circuit of claim 42,

wherein the conductor comprises a surface trace, and

wherein the electrical filter connector is a surface mount capacitor.

53. The decoupling circuit of claim 48, wherein the area encompassed by the receiver loops is determined to minimize the potential coupling of the receiver loops with the external field.

54. The decoupling circuit of claim 42, wherein the electrical filter circuit comprises one or more capacitors selected to provide a desired capacitance while minimizing parasitic inductance in the electrical filter circuit.

55. The decoupling circuit of claim 42, wherein the first and second receiver loops are constructed and arranged such that an external field electrostatically, magnetically and/or electromagnetically coupled to the first receiver loop will also be similarly coupled to the second receiver loop.

56. A printed circuit board comprising:

a printed wiring board;

an interconnect post mounted on the printed wiring board;

a ground plane within the printed wiring board;

an electrical filter circuit mounted on the printed wiring board and electrically connected to the interconnect post;

a plurality of ground lands radially spaced around and electrically connected to the electrical filter circuit, at least one of which is electrically connected to the filter circuit; and

a conductive coating adhered to surfaces of the electrical filter circuit,

wherein the electrical filter circuit shunts conducted interfering signals traveling through the interconnect post to the ground plane via the at least one ground land.

57. The printed circuit board of claim 56, wherein the electrical filter circuit, interconnect post, first ground land, ground plane, and interconnecting traces form a first receiver loop capable of being coupled to an external field that induces an interfering signal in at least one of the traces of the first receiver loop.

58. The printed circuit board of claim 57, wherein the conductive coating, first ground land, electrical filter components and interconnecting traces form a second receiver loop

adapted to be coupled to the external field which induces a signal in the second receiver loop that cancels the interfering signal induced in the at least one trace of the first receiver loop.

59. The printed circuit board of claim 56, wherein the interconnect post comprises one of the group consisting of a signal connector, a power connector and a power post.

60. The printed circuit board of claim 58, wherein the external field is electrostatically, magnetically or electromagnetically coupled with the receiver loops.

61. The printed circuit board of claim 58,

wherein the at least one trace comprises a surface trace, and

wherein the electrical filter connector is a surface mount capacitor.

62. The printed circuit board of claim 56, wherein the electrical filter circuit comprises:

one or more lumped, distributed or dissipative elements having a frequency characteristic suitable for decoupling the conducted interfering signal from a transmitted signal.