Imaging with gate controlled charge storage

• US 20050040393A1
• Filed: 08/22/2003
• Published: 02/24/2005
• Est. Priority Date: 08/22/2003
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Hong, Sungkwon C.
• Granted Patent: US 7,115,923 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and low charge loss. The charge storage region is adjacent to a gate of a transistor. The transistor gate is adjacent to the photo-conversion device and, in conjunction with the control gate, transfers photo-generated charge from the photo-conversion device to the charge storage region.

Claims

1. A pixel cell comprising:

a photo-conversion device that generates charge;

a gate controlled charge storage region that stores the charge under control of a control gate, and

a first transistor having its gate between the photo-conversion device and the charge storage region for transferring charge from the photo-conversion device to the charge storage region.

2. The pixel cell of claim 1, wherein the charge storage region is part of a buried channel MOS capacitor.

3. The pixel cell of claim 1, wherein the charge storage region is below a surface of the substrate.

4. The pixel cell of claim 1, wherein the charge storage region comprises:

a doped region of a second conductivity type; and

a doped surface layer of a first conductivity type over and in contact with the doped region of a second conductivity type, the control gate being over the doped surface layer.

5. The pixel cell of claim 1, wherein the control gate comprises polysilicon doped with a first conductivity type dopant.

6. The pixel cell of claim 1, wherein the first transistor is a shutter transistor for determining an integration time for the pixel cell.

10. The pixel cell of claim 1, wherein the photo-conversion device is a pinned photodiode.

7. A pixel cell comprising:

a photo-conversion device that generates charge;

a gate controlled charge storage region that stores the charge under control of a control gate,

a first transistor having its gate between the photo-conversion device and the charge storage region for transferring charge from the photo-conversion device to the charge storage region;

a sensing node; and

a second transistor having its gate between the charge storage region and the sensing node.

8. The pixel cell of claim 7, wherein the sensing node is a floating diffusion region.

9. The pixel cell of claim 7, wherein the control gate at least partially overlaps the first and second transistor gates.

11. A pixel cell comprising:

a photo-conversion device that generates charge;

a gate controlled charge storage region that stores the charge under control of a control gate, wherein the charge storage region comprises a doped region of a second conductivity type and a doped surface layer of a first conductivity type over and in contact with the doped region of a second conductivity type, and wherein the control gate is over the doped surface layer; and

a first transistor having its gate between the photo-conversion device and the charge storage region for transferring charge from the photo-conversion device to the charge storage region.

12. The pixel cell of claim 11, wherein the charge storage region is part of a buried channel metal oxide semiconductor (MOS) capacitor.

13. A pixel cell comprising:

a photo-conversion device that generates charge,

a gate controlled charge storage region that stores the charge under control of a control gates wherein the charge storage region comprises a doped region of a second conductivity type and a doped surface layer of a first conductivity type over and in contact with the doped region of a second conductivity types and wherein the control gate is over the doped surface layer;

a first transistor having its gate between the photo-conversion device and the charge storage region for transferring charge from the photo-conversion device to the charge storage region;

a sensing node; and

a second transistor having its gate between the charge storage region and the sensing node.

14. The pixel cell of claim 13, wherein the control gate overlaps the first and second transistor gates.

15-45. -45 (Canceled).