Semiconductor integrated circuit device and its manufacture using automatic layout

• US 20050040435A1
• Filed: 09/29/2004
• Published: 02/24/2005
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Ono, Yukichi
• Granted Patent: US 7,228,510 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring region of stripe shape elongated along a direction of row, defined on the semiconductor substrate outside of the active regions in each row, and including wirings belonging to the associated cells, each wiring region having height in a direction crossing the row direction, the wiring region having locally different height.

Claims

1-3. -3. (Cancelled)

4. A method of laying out a semiconductor integrated circuit device comprising:

(a) decomposing circuit data into cells, and reading cell data including configuration data and interconnection data;

(b) grouping cells on a semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing a direction of said row;

(c) designing a layout of wirings in said shape-fixed wiring region;

(d) designing a layout of wirings in said shape-variable wiring region;

(e) checking possible variation of wirings in said shape-variable wiring region which can reduce a distance between a pair of cells in adjacent rows; and

(f) determining if there is a variation which can reduce the distance between said pair of cells in adjacent rows, redesigning the layout of wirings in the shape-variable wiring region if there is a variation.

5. The method of laying out a semiconductor integrated circuit device according to claim 4, further including:

(g) repeating the steps of (e) and (f).

6. The method of laying out a semiconductor integrated circuit device according to claim 4, wherein said shape-variable wiring region in said step (b) has a rectangular shape of a fixed height, and the shape-variable wiring region in said steps (e) and (f) has locally variable height.

7. The method of laying out a semiconductor device according to claim 6, wherein said wirings are made of a plurality of wiring layers, and the shape-variable wiring region has locally variable height for each wiring layer.

8. The method of laying out a semiconductor integrated circuit device according to claim 4, wherein said step (e) checks density distribution of wirings in said shape-variable wiring region.

9. The method of laying out a semiconductor integrated circuit device according to claim 4, wherein said step (f) changes the order of wirings in the direction of height.

10. The method of laying out a semiconductor integrated circuit device according to claim 9, wherein said step (f) includes changing at least part of a wiring with a different wiring layer.

19. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the cell data is read from a standard cell library.

11. A method of designing a layout of a semiconductor integrated circuit device comprising:

(a) decomposing circuit data into cells, and reading cell data including configuration data and interconnection data;

(b) locating cells on a virtual semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing the direction of the row;

(c) designing a layout of wirings in said shape-fixed wiring region;

(d) designing a layout of wirings in said shape-variable wiring region;

(e) checking possible variation of wirings in said shape-variable wiring region which can reduce a distance between a pair of cells in adjacent rows; and

(f) determining if there is a variation which can reduce the distance between said pair of cells in adjacent rows, and redesigning the layout of wirings in the shape-variable wiring region if there is a variation.

12. The method of designing a layout of a semiconductor integrated circuit device according to claim 11, further including:

(g) repeating the steps of (e) and (f).

13. The method of designing a layout of a semiconductor integrated circuit device according to claim 11, wherein said shape-variable wiring region in said step (b) has a rectangular shape of a fixed height, and the shape-variable wiring region in said steps (e) and (f) has locally variable height.

14. The method of designing a layout of a semiconductor integrated circuit device according to claim 13, wherein said wirings are made of a plurality of wiring layers, and the shape-variable wiring region has locally variable height for each wiring layer.

15. The method of designing a layout of a semiconductor integrated circuit device according to claim 11, wherein said step (e) checks density distribution of wirings in said shape-variable wiring region.

16. The method of designing a layout of a semiconductor integrated circuit device according to claim 11, wherein said step (f) changes the order of wirings in the direction of height.

17. The method of designing a layout of a semiconductor integrated circuit device according to claim 16, wherein said step (f) includes changing at least part of a wiring with a different wiring layer.

20. The method of designing a layout of a semiconductor integrated circuit device according to claim 11, wherein the cell data is read from a standard cell library.

18. A computer-readable medium having encoded thereon a computer-readable program code which when executed causes a computer to:

(a) decompose circuit data into cells, and reading cell data including configuration data and interconnection data;

(b) group cells on a virtual semiconductor substrate into a plurality of rows, each of said rows including a plurality of cells aligned along a direction of a row, each cell including active regions, shape-fixed wiring regions disposed over the active regions, and shape-variable wiring regions disposed outside the active regions and having height along a direction crossing the direction of the row;

(c) design a layout of wirings in said shape-fixed wiring region;

(d) design a layout of wirings in said shape-variable wiring region;

(e) check possible variation of wirings in said shape-variable wiring region which can reduce a distance between a pair of cells in adjacent rows; and

(f) determine if there is a variation which can reduce the distance between said pair of cells in adjacent rows, and redesign the layout of wirings in the shape-variable wiring region if there is a variation.

21. The computer-readable medium according to claim 18, wherein the cell data is read from a standard cell library.