Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates

• US 20050040444A1
• Filed: 08/22/2003
• Published: 02/24/2005
• Est. Priority Date: 08/22/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cohen, Guy Moshe
• Granted Patent: US 7,355,253 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

Claims

1. A semiconductor device, comprising:

a strained-silicon channel formed adjacent a source and a drain;

a first gate formed over a first side of said channel;

a second gate formed over a second side of said channel;

a first gate dielectric formed between said first gate and said strained-silicon channel; and

a second gate dielectric formed between said second gate and said strained-silicon channel,

wherein said strained-silicon channel is non-planar.

2. The device of claim 1, wherein said strained-silicon channel thickness is substantially uniform.

3. The device of claim 1, wherein said strained-silicon channel thickness is set by epitaxial growth.

4. The device of claim 1, wherein said strained-silicon channel is substantially defect-free.

5. The device of claim 1, wherein said strained-silicon channel includes a distorted lattice cell.

6. The device of claim 1, wherein said first gate and said second gate are independently controllable.

7. The device of claim 1, wherein said strained-silicon channel comprises a fin.

8. The device of claim 1, wherein said first gate and said second gate are self-aligned.

9. The device of claim 1, wherein said first gate and said second gate are defined in a single lithographic step.

10. The device of claim 1, wherein said first gate, said second gate, said source and said drain are self-aligned with respect to each other.

11. The device of claim 7, further comprising a plurality of fins.

12. The device of claim 1, wherein said device includes a planarized top surface.

22. A circuit, comprising:

the semiconductor device of claim 1.

23. The device of claim 1, wherein said strained-silicon channel is tensely strained.

24. The device of claim 1, wherein said strained-silicon channel is compressively strained.

13. A method of forming a semiconductor device, comprising:

forming a strained-silicon channel adjacent a source and a drain;

forming a first gate over a first side of said channel;

forming a second gate over a second side of said channel;

forming a first gate dielectric between said first gate and said strained-silicon channel; and

forming a second gate dielectric between said second gate and said strained-silicon channel,

wherein said strained-silicon channel is non-planar.

14. The method of claim 13, wherein said strained-silicon channel thickness is substantially uniform.

15. The method of claim 13, wherein said strained-silicon channel thickness is set by epitaxial growth.

16. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate including a buried oxide (BOX), a silicon-on-insulator (SOI) film formed on said BOX, and a strained SiGe film formed on said SOI;

etching a cavity into said strained SiGe film, and said SOI film;

filling said cavity with a filling material to form a pedestal;

patterning said strained SiGe film and said SOI film;

etching selectively said SOI with respect to said pedestal and said SiGe film to form a free-standing SiGe structure;

relaxing said strained SiGe to form a relaxed SiGe;

fixing said relaxed SiGe to said substrate; and

epitaxially depositing a strained silicon film over said relaxed SiGe film.

17. The method of claim 16, further comprising:

depositing a first dielectric film over said strained silicon film;

depositing a first gate conductor over said first dielectric;

etching said relaxed SiGe;

depositing a second dielectric film over said strained silicon film; and

depositing a second gate conductor over said second dielectric.

18. The method of claim 16, wherein said patterning includes forming SiGe bars encapsulating one said pedestal.

19. The method of claim 16, wherein said fixing said relaxed SiGe to said substrate includes inducing strain into said relaxed SiGe.

20. The method of claim 19, wherein said inducing strain into said relaxed SiGe over-relaxes said relaxed SiGe.

21. A semiconductor device, comprising:

a strained-silicon channel formed adjacent a source and a drain;

a first gate formed over a first side of said channel;

a second gate formed over a second side of said channel;

a first gate dielectric formed between said first gate and said strained-silicon channel; and

a second gate dielectric formed between said second gate and said strained-silicon channel,

wherein said strained-silicon channel comprises a fin.

25. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate including a buried oxide (BOX), and a relaxed semiconductor film formed on said BOX;

patterning said semiconductor film;

epitaxially depositing a strained silicon film over said relaxed semiconductor film;

depositing a first dielectric film over said strained silicon film;

depositing a first gate conductor over said first dielectric film;

etching said relaxed semiconductor film;

depositing a second dielectric film over said strained silicon film; and

depositing a second gate conductor over said second dielectric film.

26. The method of claim 25, further comprising:

forming said relaxed semiconductor film on said BOX by layer transfer and bonding.

27. The method of claim 25, further comprising:

forming said relaxed semiconductor film on said BOX by elastic relaxation.