Backside metallization on microelectronic dice having beveled sides for effective thermal contact with heat dissipation devices

• US 20050040498A1
• Filed: 09/14/2004
• Published: 02/24/2005
• Est. Priority Date: 11/30/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chandran, Biju, Dias, Rajen
• Granted Patent: US 6,955,947 B2
• Time in Patent Office: Days
• US Class Current: 257/620
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10155 being other than a cuboid
• CPC Class Codes: H01L 2924/10158 at the passive surface

Abstract

A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.

Claims

1-10. -10. (Canceled)

11. A method of dicing a microelectronic device wafer, comprising:

providing a microelectronic device wafer comprising a semiconductor wafer having a back surface, said microelectronic device including at least two integrated circuit areas formed therein separated by at least one scribe street;

forming at least one substantially V-shaped notch opposing said at least one scribe street and extending from said semiconductor wafer back surface into said semiconductor wafer, wherein said substantially v-shaped notch comprises at least two sidewalls that terminate at an intersection location;

forming a metallization layer on said semiconductor wafer back surface and said at least two notch sidewalls; and

forming a channel within said at least one scribe street and extending through said interconnection layer, said semiconductor wafer, and said intersection location.

12. The method of claim 11, wherein providing said microelectronic further includes providing said microelectronic device wafer having an interconnection layer disposed on said active surface.

13. The method of claim 11, wherein forming said substantially v-shaped notch comprises forming said substantially v-shaped notch by a method selected from the group consisting of laser ablation, etching, and cutting with a wafer saw.

14. The method of claim 11, wherein forming said metallization layer on said semiconductor wafer back surface and said at least two notch sidewalls comprises depositing at least one layer of metal selected from the group consisting of gold, silver, chromium, titanium, tungsten, vanadium, and nickel.

15. A method of fabricating a microelectronic device assembly, comprising:

providing a microelectronic die having an active surface, a back surface, and at least one side, wherein said at least one microelectronic die side comprises at least one beveled sidewall and at least one channel sidewall;

disposing a metallization layer on said microelectronic die back surface and said at least one beveled sidewall; and

attaching a heat dissipation device to said microelectronic die back surface with a thermal interface material.

16. The method of claim 15, wherein disposing said metallization layer comprises disposing at least one metal selected from the group consisting of gold, silver, chromium, titanium, tungsten, vanadium, and nickel on said microelectronic die back surface and said at least one beveled sidewall.

17. The method of claim 15, wherein attaching said heat dissipation device comprises attaching said heat dissipation device with a thermal interface material selected from the group consisting of lead, tin, indium, silver, copper, and alloys thereof.

18. The method of claim 15, wherein attaching said heat dissipation device comprises attaching said heat dissipation device with said thermal interface material such that a portion of a fillet of said thermal interface material extends from said metallization layer on said at least one beveled sidewall to said heat dissipation device.

19. The method of claim 15, wherein providing said microelectronic die comprises:

providing a microelectronic device wafer comprising a semiconductor wafer having a back surface, said microelectronic device including at least two integrated circuit areas formed therein separated by at least one scribe street;

forming at least one substantially V-shaped notch opposing said at least one scribe street and extending from said semiconductor wafer back surface into said semiconductor wafer, wherein said substantially v-shaped notch comprises at least two sidewalls that terminate at an intersection location;

forming a metallization layer on said semiconductor wafer back surface and said at least two notch sidewalls; and

forming a channel within said at least one scribe street and extending through said interconnection layer, said semiconductor wafer, and said intersection location.

20. The method of claim 19, wherein providing said microelectronic die further includes providing said microelectronic device wafer having an interconnection layer disposed on said active surface.

21. The method of claim 19, wherein forming said substantially v-shaped notch comprises forming said substantially v-shaped notch by a method selected from the group consisting of laser ablation, etching, and cutting with a wafer saw.

22. The method of claim 19, wherein forming said metallization layer on said semiconductor wafer back surface comprises depositing at least one layer of metal selected from the group consisting of gold, silver, chromium, titanium, tungsten, vanadium, and nickel.