Low voltage to high voltage level shifter and related methods

• US 20050040854A1
• Filed: 08/18/2004
• Published: 02/24/2005
• Est. Priority Date: 08/22/2003
• Status: Active Grant

• Current Assignee: Idaho Research Foundation, Inc.
• Original Assignee: Idaho Research Foundation, Inc.
• Inventors: Cox, David F., Buck, Kevin M., Hess, Herbert L., Mentze, Erik J.
• Granted Patent: US 7,112,995 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

Claims

1. A shifter circuit comprising:

a high voltage buffer stage comprising;

multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, the transistor stack being connected between a voltage level being shifted to and an input voltage; and

an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack;

a low voltage buffer stage having an input connected to said input voltage, and an output, the low voltage buffer stage being operably connected to the high voltage buffer stage and being connected between a voltage level being shifted away from and a lower voltage; and

an output buffer stage driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

2. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the p-channel devices are connected between the n-channel devices and the voltage level being shifted to.

3. The shifter circuit of claim 1, wherein the inverter comprises p-channel and n-channel devices.

4. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device.

5. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and wherein the said inverter inputs are connected across at least one common p-channel device.

6. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and wherein the input of the inverter'"'"'s p-channel device is connected to an intermediate node between two p-channel devices.

7. The shifter circuit of claim 1, wherein the transistor stack comprises p-channel and n-channel devices, and wherein the inverter comprises p-channel and n-channel devices, and wherein one input of the inverter is connected to an intermediate node between two p-channel devices, and another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and wherein the input of the inverter'"'"'s p-channel device is connected to the intermediate node between the two p-channel devices, and wherein the input of the inverter'"'"'s n-channel device is connected between the intermediate node between the p-channel device and the n-channel device.

8. The shifter circuit of claim 1, wherein the transistors of the transistor stack comprise gate/drain connected MOSFETs.

9. A shifter circuit comprising:

a high voltage buffer stage comprising;

multiple transistor stacks, each of which comprising multiple transistors having a plurality of intermediate nodes connecting individual transistors along a respective stack, each transistor stack being connected between a voltage level being shifted to and an input voltage; and

multiple inverters each of which comprising multiple inputs and an output, each inverter being connected with an individual respective one of the transistor stacks, individual inverter inputs being connected to a respective intermediate node of its connected transistor stack;

a low voltage buffer stage having an input connected to said input voltage and an output, the low voltage buffer stage being operably connected to the high voltage buffer stage and being connected between a voltage level being shifted away from and a lower voltage; and

an output buffer stage driven by the output of a high voltage buffer stage inverter and the output of the low voltage buffer stage.

10. The shifter circuit of claim 9, wherein each transistor stack comprises p-channel and n-channel devices, and wherein the p-channel devices of a stack are connected between the n-channel devices of the stack and the voltage level being shifted to.

11. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices.

12. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:

one input of its associated inverter is connected to an intermediate node between two p-channel devices, and

another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device.

13. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:

one input of its associated inverter is connected to an intermediate node between two p-channel devices,

another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and

wherein the said inverter inputs are connected across at least one common p-channel device.

14. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:

one input of its associated inverter is connected to an intermediate node between two p-channel devices,

another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and

wherein the input of the inverter'"'"'s p-channel device is connected to the intermediate node between the two p-channel devices.

15. The shifter circuit of claim 9, wherein said inverters each comprise p-channel and n-channel devices, and wherein, for each transistor stack:

one input of its associated inverter is connected to an intermediate node between two p-channel devices,

another input of the inverter is connected to a intermediate node between a p-channel device and an n-channel device, and

wherein the input of the inverter'"'"'s p-channel device is connected to the intermediate node between the two p-channel devices, and wherein the input of the inverter'"'"'s n-channel device is connected between the intermediate node between the p-channel device and the n-channel device.

16. The shifter circuit of claim 9, wherein the transistors of each transistor stack comprise gate/drain connected MOSFETs.

17. The shifter circuit of claim 9, wherein said low voltage buffer stage comprises multiple low voltage buffer stages cascaded together.

18. A method comprising:

supplying a voltage level away from which a shift is desired;

supplying a voltage level to which a shift is desired;

supplying an input voltage; and

shifting the input voltage, using said voltage levels and a circuit comprising;

a high voltage buffer stage comprising;

multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack, the transistor stack being connected between the voltage level being shifted to and the input voltage; and

an inverter comprising multiple inputs and an output, individual inverter inputs being connected to a respective intermediate node of the transistor stack;

a low voltage buffer stage having an input connected to said input voltage and an output, the low voltage buffer stage being operably connected to the high voltage buffer stage and being connected between said voltage level being shifted away from and a lower voltage; and

an output buffer stage driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

19. The method of claim 18, wherein said high voltage buffer stage comprises multiple transistor stacks and multiple inverters, each transistor stack being associated with an inverter.

20. The method of claim 18, wherein said low voltage buffer stage comprises multiple low voltage buffer stages cascaded together.