LDMOS and CMOS integrated circuit and method of making

• US 20050041070A1
• Filed: 09/28/2004
• Published: 02/24/2005
• Est. Priority Date: 03/26/2001
• Status: Active Grant

• Current Assignee: Bao-Sung Bruce Yeh, Cathy P. Peltier, Wang S. Jonathan, Zhizang Chen
• Original Assignee: Bao-Sung Bruce Yeh, Cathy P. Peltier, Wang S. Jonathan, Zhizang Chen
• Inventors: Peltier, Cathy P., Bruce Yeh, Bao-Sung, Chen, Zhizang, Wang, S. Jonathan
• Granted Patent: US 6,902,258 B2
• Time in Patent Office: Days
• US Class Current: 347/63
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (V_t) implant.

Claims

1. An integrated circuit on a substrate, comprising:

a first well having a first dopant concentration and including a second conductivity type low-voltage transistor;

a second well having a dopant concentration equal to the first dopant concentration and including a first conductivity type high-voltage transistor;

a third well having a second dopant concentration of an opposite type than the first well and including a first conductivity type low-voltage transistor; and

wherein the first conductivity type low-voltage transistor and the second conductivity type low-voltage transistor are created without a threshold voltage (V_t) implant.

2. The integrated circuit of claim 1, wherein the first conductivity type high-voltage transistor is a lateral dual-diffusion metal oxide semiconductor.

3. The integrated circuit of claim 2, wherein the first conductivity type high-voltage transistor has a breakdown voltage of greater than. 40 volts.

4. The integrated circuit of claim 1, further comprising an energy dissipation element coupled to said first conductivity type high-voltage transistor.

5. A fluid jet printhead, comprising:

the integrated circuit of claim 4;

and

an orifice layer defining an opening for ejecting fluid thermally coupled to said energy dissipation element, said orifice layer disposed on the surface of the integrated circuit.

6. A recording cartridge, comprising:

the fluid jet printhead of claim 5;

a body defining a fluid reservoir, said fluid reservoir fluidically coupled to the opening in said orifice layer of the fluid jet printhead; and

a pressure regulator to control the pressure of the fluid reservoir within the body of the recording cartridge.

7. A recording device for placing fluid on a medium, comprising:

the recording cartridge of claim 6;

and

a transport mechanism to move the recording cartridge in at least one direction with respect to the medium.

8. The integrated circuit of claim 1 wherein the first and second wells are an N-wells and wherein the third well is a P-well.

9. The integrated circuit of claim 1 wherein the first conductivity type high-voltage transistor is an n conductivity type high-voltage transistor.

10-17. -17. (cancelled).