Rectifying charge storage memory circuit

• US 20050041455A1
• Filed: 07/01/2003
• Published: 02/24/2005
• Est. Priority Date: 11/28/2000
• Status: Active Grant

• Current Assignee: Precision Dynamics Corporation (Brady Corporation)
• Original Assignee: Precision Dynamics Corporation (Brady Corporation)
• Inventors: Beigel, Michael L., Leipper, John I.
• Granted Patent: US 7,031,182 B2
• Time in Patent Office: Days
• US Class Current: 365/105
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A composite rectifying charge storage device, consisting of a rectifier and capacitor which share common elements, is provided in a memory circuit or memory cell. In one form, the memory cell is adapted for alternative operation as a random access memory (RAM) or as a read only memory (ROM).

Claims

1. A memory circuit, comprising;

at least one memory cell including a word line and a bit line; and

a composite rectifying charge storage device within said memory cell and coupled between said word line and said bit line;

said composite rectifying charge storage device comprising a rectifier component fabricated with a common conductor forming a side of the rectifier component, and a capacitor component fabricated as a single unitary structure with the rectifier component such that the capacitor component incorporates the common conductor of the rectifier component as a side of the capacitor component, the capacitor component to receive rectified current from the rectifier component over the common conductor.

2. The memory circuit of claim 1, wherein said at least one memory cell comprises a matrix of memory cells each coupled to a respective pair of word and bit lines and each having a composite rectifying charge storage device therein.

3. The memory circuit of claim 1, wherein said rectifier component is coupled to said word line and said capacitor component is coupled to said bit line.

4. The memory circuit of claim 1, wherein said rectifier component is coupled to said bit line and said capacitor component is coupled to said word line.

5. The memory circuit of claim 1, wherein said rectifier component comprises a diode component.

6. The memory circuit of claim 5, wherein said diode component is forward-bias oriented relative to said capacitor component.

7. The memory circuit of claim 5, wherein said diode component is reverse-bias oriented relative to said capacitor component.

8. The memory circuit of claim 5, wherein said at least one memory cell further includes a state line for programming said diode component in a selected one of substantially conductive and substantially nonconductive states.

9. The memory circuit of claim 1, wherein said capacitor component comprises said common conductor, a second conductor, and a dielectric material disposed therebetween.

10. The memory circuit of claim 9, wherein said common conductor is coupled to one of said word line and said bit line, and said second conductor is coupled to ground.

11. The memory circuit of claim 9, wherein said at least one memory cell further includes a state line coupled to one of said common conductor and said second conductor.

12. The memory circuit of claim 1, further including a gate element coupled between said composite rectifying charge storage device and said word line.

13. The memory circuit of claim 12, wherein said gate element comprises a gate transistor.

14. The memory circuit of claim 12, wherein said gate element comprises a field effect transistor.

15. The memory circuit of claim 1, further including a gate transistor having a gate junction coupled to said word line, and source and drain junctions coupled between said bit line and said composite rectifying charge storage device.

16. The memory circuit of claim 15, wherein said capacitor component comprises said common conductor, a second conductor, and a dielectric material disposed therebetween, said source and drain junctions of said gate transistor being coupled between said bit line and said second conductor, said rectifier component being coupled to ground.

17. The memory circuit of claim 1, further including a gate element coupled between said composite rectifying charge storage device and said word line, and a RAM enable element coupled to said composite rectifying charge storage device for selectively setting said rectifier component in a selected one of substantially conductive and substantially nonconductive states.

18. The memory circuit of claim 17, wherein said gate element comprises a gate transistor, and wherein said RAM enable element comprises a RAM enable transistor.

19. The memory circuit of claim 17, wherein said rectifier component comprises an irreversible state diode component.

20. The memory circuit of claim 17, wherein said rectifier component comprises a reversible state diode component.

21. The memory circuit of claim 1, wherein said rectifier and capacitor components are carried on a common substrate.

22. The memory circuit of claim 21, wherein said common substrate is a flexible substrate.

23. The memory circuit of claim 21, wherein said capacitor structure incorporates said common substrate.

24. The memory circuit of claim 1, further including a gate transistor fabricated as a single unitary structure with said composite rectifying charge storage device.

25. The memory circuit of claim 24, further including a RAM enable transistor fabricated as a single unitary structure with said composite rectifying charge storage device and said gate transistor.

26. The memory circuit of claim 1, further including a RAM enable transistor fabricated as a single unitary structure with said composite rectifying charge storage device.

27. A memory circuit, comprising:

at least one memory cell including a word line and a bit line;

a rectifier component;

a common conductor connected to one side of said rectifier; and

a capacitor component incorporating said common conductor;

said rectifier and capacitor components being coupled between said word line and said bit line;

said rectifier component, common conductor and capacitor component comprising a unitary element.

28. The memory circuit of claim 27, wherein said at least one memory cell comprises a matrix of memory cells each coupled to a respective pair of word and bit lines.

29. The memory circuit of claim 27, wherein said rectifier component is coupled to one of said word line and said bit line, and wherein said capacitor component is coupled to the other of said word line and said bit line.

30. The memory circuit of claim 27, wherein said rectifier component comprises a diode component.

31. The memory circuit of claim 30, wherein said diode component is forward-bias oriented relative to said capacitor component.

32. The memory circuit of claim 30, wherein said diode component is reverse-bias oriented relative to said capacitor component.

33. The memory circuit of claim 30, wherein said at least one memory cell further includes a state line for programming said diode component in a selected one of substantially conductive and substantially nonconductive states.

34. The memory circuit of claim 27, wherein said capacitor component comprises said common conductor, a second conductor, and a dielectric material disposed therebetween.

35. The memory circuit of claim 34, wherein said common conductor is coupled to one of said word line and said bit line, and said second conductor is coupled to ground.

36. The memory circuit of claim 34, wherein said at least one memory cell further includes a state line coupled to one of said common conductor and said second conductor.

37. The memory circuit of claim 27, further including a gate element coupled between one of said rectifier and capacitor components and said word line.

38. The memory circuit of claim 27, further including a gate transistor having a gate junction coupled to said word line, and source and drain junctions coupled between said bit line and one of said rectifier and capacitor components.

39. The memory circuit of claim 38, wherein said capacitor component comprises said common conductor, a second conductor, and a dielectric material disposed therebetween, said source and drain junctions of said gate transistor being coupled between said bit line and said second conductor, said rectifier component being coupled to ground.

40. The memory circuit of claim 38, further including a RAM enable transistor coupled to said rectifier component for selectively setting said rectifier component in a selected one of substantially conductive and substantially nonconductive states.

41. The memory circuit of claim 40, wherein said rectifier component comprises an irreversible state diode component.

42. The memory circuit of claim 40, wherein said rectifier component comprises a reversible state diode component.

43. The memory circuit of claim 27, wherein said rectifier and capacitor components are carried on a common substrate.

44. The memory circuit of claim 43, wherein said common substrate is a flexible substrate.

45. The memory circuit of claim 43, wherein said capacitor structure incorporates said common substrate.

46. The memory circuit of claim 27, further including a gate transistor;

said rectifier component, common conductor, capacitor component and gate transistor comprising a unitary element.

47. The memory circuit of claim 27, further including a RAM enable transistor;

said rectifier component, common conductor, capacitor component, gate transistor and RAM enable transistor comprising a unitary element.

48. The memory circuit of claim 27, further including a RAM enable transistor;

said rectifier component, common conductor, capacitor component and RAM enable transistor comprising a unitary element.

49. A memory circuit, comprising:

at least one memory cell including a word line and a bit line;

a rectifier component;

a common conductor connected to one side of said rectifier;

a capacitor component incorporating said common conductor; and

a gate transistor coupled between one of said rectifier and capacitor components and said word line;

said rectifier component, common conductor, capacitor component and gate transistor comprising a unitary element.

50. The memory circuit of claim 49, further including a RAM enable transistor coupled to said rectifier component for selectively setting said rectifier component in a selected one of substantially conductive and substantially nonconductive states;

said rectifier component, common conductor, capacitor component, gate transistor and RAM enable transistor comprising a unitary element.

51. A memory circuit, comprising:

at least one memory cell including a word line and a bit line;

a rectifier component;

a common conductor connected to one side of said rectifier;

a capacitor component incorporating said common conductor;

said rectifier and capacitor components being coupled between said word line and said bit line; and

a RAM enable transistor coupled to said rectifier component for selectively setting said rectifier component in a selected one of substantially conductive and substantially nonconductive states;

said rectifier component, common conductor, capacitor component and said RAM enable transistor comprising a unitary element.

52. A memory circuit, comprising;

a matrix of memory cells each coupled to and separately addressable by a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit lines; and

a plurality of composite rectifying charge storage devices each disposed within a respective one of said memory cells and coupled between the word line and bit line associated with said one of said memory cells;

each of said composite rectifying charge storage devices comprising a rectifier component fabricated with a common conductor forming a side of the rectifier component, and a capacitor component fabricated as a single unitary structure with the rectifier component such that the capacitor component incorporates the common conductor of the rectifier component as a side of the capacitor component, the capacitor component to receive rectified current from the rectifier component over the common conductor.

53. The memory circuit of claim 52, wherein each of said memory cells further includes a gate element coupled between said composite rectifying charge storage device and said word line, and a RAM enable element coupled to said composite rectifying charge storage device for selectively setting said rectifier component in a selected one of substantially conductive and substantially nonconductive states.

54. The memory circuit of claim 53, wherein said gate element comprises a gate transistor, and wherein said RAM enable element comprises a RAM enable transistor.

55. The memory circuit of claim 53, wherein said rectifier component comprises an irreversible state diode component.

56. The memory circuit of claim 53, wherein said rectifier component comprises a reversible state diode component.

57. The memory circuit of claim 54, wherein said gate transistor of each of said memory cells is fabricated as a single unitary structure with the associated composite rectifying charge storage device.

58. The memory circuit of claim 57, further wherein the RAM enable transistor of each of said memory cells is fabricated as a single unitary structure with the associated composite rectifying charge storage device.