Circuit and method for evaluating and controlling a refresh rate of memory cells of a dynamic memory

• US 20050041502A1
• Filed: 08/18/2004
• Published: 02/24/2005
• Est. Priority Date: 08/18/2003
• Status: Active Grant

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Perner, Martin
• Granted Patent: US 7,057,961 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning

Abstract

A circuit for controlling a refresh rate of memory cells of a dynamic memory includes a control circuit for controlling an access to memory cells of the dynamic memory. A memory circuit can be driven by the control circuit and stores a time information item with regard to an access to a memory cell assigned to the time information item. The control circuit can be operated in a supervisory operating mode such that a time information item is written to the memory circuit by the control circuit in the event of an access to the assigned memory cell. The time information item is read out in the event of a subsequent access to the assigned memory cell.

Claims

1. A circuit for evaluating and controlling a refresh rate of memory cells of a dynamic memory, comprising:

a control circuit for controlling access to memory cells of the dynamic memory, the dynamic memory operating in a plurality of operating modes; and

a memory circuit, the memory circuit being driven by the control circuit, the memory circuit storing a time information item with regard to an access to a memory cell assigned to the time information item,

wherein, in the event of an access to the assigned memory cell, the control circuit operating in a supervisory operating mode such that a time information item is written to the memory circuit by the control circuit,

the time information item being read out in the event of a subsequent access to the assigned memory cell,

the read-out time information item being transferred to an evaluation circuit, and an evaluation information item with regard to the time duration between individual accesses to the assigned memory cell being output from the memory.

2. The circuit as claimed in claim 1, wherein

the evaluation circuit for determining the evaluation information item performs a comparison of the time information item stored in the memory circuit with a reference time information item and calculates a difference therefrom, the evaluation circuit having a memory unit for storing individual values of a plurality of successively determined evaluation information items, and

the evaluation circuit designed to output the content of the memory unit to outside the memory.

3. The circuit as claimed in claim 2, wherein the evaluation circuit can be connected to data terminal pins of the dynamic memory.

4. The circuit as claimed in claim 1, wherein the circuit has a counter register and an oscillator, the oscillator being connected to the counter register, the oscillator incrementing or decrementing the counter register with a defined clock rate, the counter register being connected to the memory circuit for writing in the time information item.

5. The circuit as claimed in claim 4, wherein the reference time information item can be tapped off at the counter register for comparison with the time information item stored in the memory circuit.

6. The circuit as claimed in claim 4, wherein the counter register can be set or reset by an operating mode signal.

7. The circuit as claimed in claim 1, wherein the memory circuit is formed by memory cells arranged in a memory area along an addressable word line of the dynamic memory.

8. The circuit as claimed in claim 1, wherein the memory circuit has a memory area for storing a control bit, the control bit being set depending on the stored time information item and can be read out by the control circuit.

9. The circuit as claimed in claim 1, wherein the circuit is arranged on one of a plurality of memory chips, the plurality of memory chips forming a memory module arrangement, one of the memory chips being connected into a signal and data path of the rest of the memory chips in order to evaluate and control the refresh rate of memory cells.

10. A method for evaluating and controlling a refresh rate of memory cells of a dynamic memory, the method comprising:

assigning a time information item with regard to an access to at least one of the memory cells to a memory circuit;

in a supervisory operating mode of the memory, storing the time information item in the event of an access to the assigned memory cell and reading out the time information item in the event of a subsequent access to the assigned memory cell; and

feeding the read-out time information item to an external evaluation that yields an evaluation information item with regard to the time duration between individual accesses to the assigned memory cell.

11. The method as claimed in claim 10, wherein individual extrema are determined from a totality of a plurality of evaluation information items with regard to a plurality of memory cells.

12. The method as claimed in claim 11, wherein the dynamic memory has a plurality of word lines and at least one memory area in which a plurality of the word lines are arranged, a plurality of the memory cells in each case being selectable by the word lines, the memory cells being accessed in units of word lines by a serial selection of word lines within the memory area, individual accesses and corresponding evaluations being carried out until a word line is reached at a set marker of the memory area.

13. The method as claimed in claim 12, wherein, when a word line reaches the set marker of the memory area, a serial selection of word lines is effected within a further, different memory area.

14. The method as claimed in claim 10, wherein for accessing memory cells of the dynamic memory, an activation command is generated for the selection and activation of a word line of the memory and a precharge command is generated for precharging the word line after the activation,

reading out a stored time information item of the assigned memory cell, selected with the activated word line by the activation command, and

storing a new time information item of the assigned memory cell by the precharge command.

15. The method as claimed in claim 10, wherein in a plurality of different operating modes for accessing memory cells of the memory, an activation command is generated for selection and activation of a word line of the memory and a precharge command is generated for precharging the word line after the activation, and

a selection is made in respect of that one of the operating modes in which the supervisory operating mode of the memory is activated for recording the time information item.

16. The method as claimed in claim 10, wherein, in an initialization operation of the memory, preallocating a value for the memory circuit or parts thereof before the circuit enters into the supervisory operating mode.

17. The method as claimed in claim 10, wherein a control bit is set depending on the respective time information item stored in the memory circuit and is read out to ascertain whether a time information item has previously been written.