Periodic interface calibration for high speed communication
First Claim
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1. A signal interface, comprising:
- a set of signal lines having N+1 signal lines, where N is an integer;
N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of n+1 signal paths with the set of signal lines;
an n line bus;
a line maintenance circuit; and
a switch in the n+1 signal paths, and control logic for the switch, which selectively routes n signal paths in the set to the n line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of n+1 signal paths while enabling data flow on n signal paths in the set to the n line bus;
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Abstract
A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the N line bus. The communication line on which the maintenance operation is performed, is changed after the operation is complete, so that all of the N+1 communication lines are periodically maintained, without interfering with communications on N of the N+1 communication lines.
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Citations
49 Claims
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1. A signal interface, comprising:
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a set of signal lines having N+1 signal lines, where N is an integer;
N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of n+1 signal paths with the set of signal lines;
an n line bus;
a line maintenance circuit; and
a switch in the n+1 signal paths, and control logic for the switch, which selectively routes n signal paths in the set to the n line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of n+1 signal paths while enabling data flow on n signal paths in the set to the n line bus;
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A signal interface, comprising:
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an N line bus;
a set of signal lines having N+1 signal lines, where N is an integer;
N+1 transmitters coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines;
a line maintenance circuit; and
a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set from the N line bus to N signal lines in the set of signal lines, and routes signal path (n) in the set from the line maintenance circuit to signal line (n) in the set of signal lines, where (n) is changed according to a pattern to selectively perform maintenance on signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set from the N line bus. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A communication system for inter-chip signals, comprising:
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a first integrated circuit, a second integrated circuit, and a set of N+1 communications lines between the first and second integrated circuits;
the first integrated circuit comprising a first N line bus, where N is an integer;
a set of signal lines having N+1 signal lines coupled to respective communications lines in the set of N+1 communications lines;
N+1 transmitters coupled to respective signal lines in the set of signal lines establishing a set of N+1 transmitter signal paths with the set of signal lines;
a calibration signal source; and
a switch in the N+1 transmitter signal paths, and first control logic for the switch, which selectively routes N transmitter signal paths in the set from the N line bus to N transmitter signal lines in the set of signal lines, transmitter signal path (n) in the set from the calibration signal source to one transmitter signal line in the set of transmitter signal lines, where (n) is changed according to a pattern to selectively supply calibration signals on communication lines in the set of N+1 communication lines while enabling data flow on N communication lines in the set from the N line bus; and
the second integrated circuit comprising a set of signal lines having N+1 signal lines coupled to respective communications lines in the set of N+1 communications lines;
N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of N+1 receiver signal paths with the set of signal lines;
a second N line bus;
a calibration circuit; and
a switch in the N+1 receiver signal paths, and second control logic for the switch, which selectively routes N receiver signal paths in the set to the second N line bus and receiver signal path (n) in the set to the calibration circuit, where (n) is changed according to the pattern to selectively calibrate receiver signal paths in the set of N+1 receiver signal paths while enabling data flow on N receiver signal paths in the set to the second N line bus. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A method for managing a high speed communication interface for a parallel bus having N bus lines, where N is an integer, comprising:
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establishing N+1 communication lines;
performing a maintenance operation on communication line (n) of the N+1 communications lines and enabling paths from the N bus lines on N of the N+1 communications lines;
after performing the maintenance operation on communication line (n) of the N+1 communications lines, changing (n) and performing a maintenance operation a next communication line of the N+1 communication lines. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A signal interface, comprising:
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a set of signal lines;
a set of receivers coupled to respective signal lines in the set of signal lines;
a bus comprising a set of bus lines;
a line maintenance circuit; and
a switch coupled to the set of receivers, to the bus and to the line maintenance circuit, and control logic for the switch, which selectively routes signals in parallel from receivers in the set of receivers to bus lines in the set of bus lines and to the line maintenance circuit, where the receiver in the set of receivers routed to the line maintenance circuit is changed according to a pattern to selectively maintain signal paths over said set of signal lines.
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48. A transmission circuit on an integrated circuit, comprising:
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a line maintenance circuit to output a line maintenance signal;
a set of transmitters coupled to receive a first set of signals and the line maintenance signal, and to output a second set of signals, wherein the second set of signals includes the first set of signals and the maintenance signal; and
a switch coupled to the set of transmitters and a control logic for the switch, to selectively route the first set of signals and the line maintenance signal in parallel to the set of transmitters, where the transmitter in the set of transmitters routed to by the line maintenance circuit is changed according to a pattern to selectively maintain the second set of signals from the set of transmitters and to permit the maintenance signal to be used as a calibration signal.
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49. A receiver circuit on an integrated circuit, comprising:
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means for receiving a first set of signals and a line maintenance signal, and to output a second set of signals;
means for calibrating the means for receiving, the means for calibrating coupled to receive the line maintenance signal;
means for routing the first set of signals and the line maintenance signal in parallel from the means for receiving, wherein the routing changes according to a pattern to selectively maintain the second set of signals and to permit the maintenance signal to be used as a maintenance signal for maintaining different portions of the means for receiving.
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Specification