I/Q demodulation circuit

• US 20050041759A1
• Filed: 08/17/2004
• Published: 02/24/2005
• Est. Priority Date: 08/18/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakano, Yoshiaki
• Granted Patent: US 7,480,348 B2
• Time in Patent Office: Days
• US Class Current: 375/324
• CPC Class Codes: H04L 2027/0016 Stabilisation of local oscillators
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 27/3863 Compensation for quadrature error in the received signal

Abstract

In an I/Q demodulation circuit, an offset amount determined in an offset detection mode is previously stored so that, in a normal reception mode, an offset is corrected for based on the data thus stored. With this configuration, a DC offset and a phase offset can be corrected for without a delay in an I/Q demodulation operation.

Claims

1. An I/Q demodulation circuit comprising:

an I/Q demodulator for producing an analog I/Q signal by multiplying an input signal by a local oscillation signal;

an analog-to-digital converter for converting the analog I/Q signal into a digital I/Q signal;

a reference sinusoidal-wave signal generator for producing a predetermined reference sinusoidal-wave signal;

a selector for selecting and feeding to the I/Q demodulator one of an external input signal and the reference sinusoidal-wave signal;

an offset amount detection circuit for detecting a DC offset amount and a phase offset amount of the digital I/Q signal obtained when the reference sinusoidal-wave signal is selected;

a storage circuit for storing a result of detection by the offset amount detection circuit or a correction value with which to correct for the result; and

an offset correction circuit for correcting for, based on data stored in the storage circuit, a DC offset and a phase offset of the digital I/Q signal obtained when the external input signal is selected.

2. The I/Q demodulation circuit of claim 1,

wherein the offset amount detection circuit includes:

a delay circuit for producing a delayed inverted signal by delaying, of two versions of the digital I/Q signal differentially fed thereto, an inverted digital I/Q signal by half a period; and

a subtraction circuit for determining the DC offset amount by subtracting the delayed inverted signal from a non-inverted digital I/Q signal.

3. The I/Q demodulation circuit of claim 1, further comprising:

a controlled circuit for subtracting from the digital I/Q signal a DC offset amount conforming to an instruction from the offset correction circuit.

4. The I/Q demodulation circuit of claim 1, further comprising:

a controlled circuit for varying a DC potential of the analog I/Q signal according to an instruction from the offset correction circuit.

5. The I/Q demodulation circuit of claim 1,

wherein the offset amount detection circuit includes:

a calculation circuit for calculating a square sum of the digital I/Q signal;

a DC cut circuit for extracting only an alternating-current component from an output signal of the calculation circuit; and

a signal amplitude detection circuit for determining the phase offset by detecting an amplitude of the alternating-current component.

6. The I/Q demodulation circuit of claim 1,

wherein the offset amount detection circuit includes:

a voltage comparison circuit for comparing, with respect to two versions of the digital I/Q signal differentially fed thereto, an I signal with an inverted signal thereof and a Q signal and an inverted signal thereof;

a zero-cross point detection circuit for determining a time point at which an output signal of the voltage comparison circuit becomes equal to zero; and

a calculation circuit for determining the phase offset by comparing a zero-cross point of the I signal and a zero-cross point of the Q signal shifted by half a period.

7. The I/Q demodulation circuit of claim 1,

wherein the I/Q demodulator includes:

a variable-phase controlled circuit for varying a phase of the local oscillation signal by a phase offset amount conforming to an instruction from the offset correction circuit.

8. The I/Q demodulation circuit of claim 7,

wherein the variable-phase controlled circuit includes:

an active filter of which a cutoff frequency is controlled to vary according to an instruction from the offset correction circuit.

9. The I/Q demodulation circuit of claim 1,

wherein the DC offset is corrected for before the phase offset amount is detected.

10. The I/Q demodulation circuit of claim 1,

wherein the reference sinusoidal-wave signal generator includes:

a frequency multiplier for producing the reference sinusoidal-wave signal by multiplying a frequency of the local oscillation signal.

11. The I/Q demodulation circuit of claim 1,

wherein the reference sinusoidal-wave signal generator includes:

a frequency divider for producing the reference sinusoidal-wave signal by dividing a frequency of the local oscillation signal.

12. The I/Q demodulation circuit of claim 1, further comprising:

a 1/2 frequency divider for producing two signals having half a frequency of the reference sinusoidal-wave signal and having a phase difference of 90 degrees relative to each other,

wherein an output signal of the 1/2 frequency divider is used as the local oscillation signal.

13. An I/Q demodulation circuit comprising:

an I/Q signal generation circuit for producing an l/Q signal from an input signal;

an offset amount detection circuit for detecting an offset amount of the I/Q signal; and

a storage circuit for storing the offset amount or a value with which to correct for the offset amount,

wherein an offset of the I/Q signal is corrected for based on data stored in the storage circuit.