Fluxless assembly of chip size semiconductor packages

• US 20050042838A1
• Filed: 03/01/2002
• Published: 02/24/2005
• Est. Priority Date: 03/01/2002
• Status: Active Grant

• Current Assignee: Agng, LLC
• Original Assignee: Agng, LLC
• Inventors: Garyainov, Stanislav A, Novikov, Vladimir V, Gotman, Alexander S
• Granted Patent: US 7,098,072 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

A method for assembling semiconductor packages (10) includes forming corresponding pairs of conductive pads (14, 16, 20, 22) on respective surfaces of a die (12) and an interconnective substrate (18). Each pad in each pair includes an upper portion comprising at least one component of an electrically conductive eutectic alloy. Sharp, upstanding peaks (50, 58) are formed on at least one of the pads in each pair. The die and substrate are forcefully abutted and the pads heated until the sharp peaks penetrate through oxide films (52) on the respective opposing pads in each pair and contact the upper surface of the other pad therein, thereby initiating pad fusion. The pads are then cooled to solidify the molten portions thereof into an electrically conductive joint between each corresponding pair of pads and a hermetic seal around the periphery of the package.

Claims

1. A method for soldering a first substrate (12) to and in electrical connection with a second substrate (18) without using a flux or reducing atmosphere, the method characterized by:

forming a first electrically conductive pad (14) on a first surface of the first substrate (12), the first pad including an upper portion comprising at least one component of an electrically conductive eutectic alloy;

forming a corresponding second pad (16) on a first surface of the second substrate (18), the second pad including an upper portion comprising at least one other component of the eutectic alloy;

forming at least one sharp upstanding peak (50, 58) on an upper surface of at least one of the first and second pads (14, 16);

urging the respective first surfaces of the first and second substrates (12, 18) toward each other such that the respective upper surfaces of the first and second pads (14, 16) are brought together in a forceful opposing abutment with each other;

heating the opposing pads (14, 16) to at least the soldering temperature of the eutectic alloy and until the at least one sharp upstanding peak (50, 58) on the at least one pad penetrates through any oxide films (52) on the respective upper surfaces of the pads and contacts the upper surface of the opposing other pad, thereby initiating melting and dissolution of the respective upper portions of the opposing pads into each other; and

,

cooling the opposing pads to solidify the dissolved, molten upper portions thereof into an electrically conductive joint between the pads.

2. The method of claim 1, wherein:

the first substrate (12) comprises a semiconductor die;

the first pad (14) comprises one or more signal input/output pads of the die;

the second substrate (18) comprises an interconnective substrate of a semiconductor package (10); and

,

the second pad (16) comprises one or more signal connection pads of the interconnective substrate (18),

whereby the die (12) is electrically interconnected with the substrate (18).

3. The method of claim 2, wherein:

the first pad (14) further comprises a frame (20) around a periphery of the first surface of the die (12); and

,

the second pad (16) further comprises a corresponding frame (22) around a periphery of the first surface of the interconnective substrate (18),

whereby a space (36) inside of the frames (20, 22) and between the respective first surfaces of the die (12) and the substrate (18) is closed and hermetically sealed from the surrounding ambient simultaneously with the electrical interconnection of the die with the substrate.

4. The method of any one of claims 1-3, wherein the at least one eutectic alloy components are selected from the group consisting of:

Gold (Au);

aluminum (Al);

germanium (Ge);

zinc (Zn);

silicon (Si);

cadmium (Cd);

tin (Sn);

copper (Cu);

bismuth (Bi);

silver (Ag); and

, lead (Pb).

5. The method of any one of claims 1-3, wherein at least one of the respective upper portions of the first and the second pads (14, 16, 20, 22) is formed by a vacuum deposition process or an electroplating process.

6. The method of any one of claims 1-3, wherein the at least one sharp upstanding peak (50, 58) is formed by a vacuum deposition process.

7. The method of any one of claims 1-3, wherein the heating is effected with a laser.

8. The method of any one of claims 1-3, wherein forming the at least one sharp peak (50, 58) is characterized by:

forming a lower portion (42, 44, 46, 48) of the at least one pad (14, 16, 20, 22), the lower portion comprising a metal or a semiconductor;

forming a coating (56) on an upper surface of the lower portion of the at least one pad, the coating consisting of the same at least one eutectic alloy component comprising the upper portion of the at least one pad; and

,

forming the at least one peak (50, 58) on an upper surface of the coating (56), the at least one peak consisting of the same at least one eutectic alloy component comprising the upper portion of the at least one pad.

9. The method of any one of claims 1-3, wherein forming the at least one sharp peak (50, 58) is characterized by:

forming a lower portion (42, 44, 46, 48) of the at least one pad (14, 16, 20, 22), the lower portion comprising a metal or a semiconductor;

forming the at least one peak (50, 58) on an upper surface of the lower portion of the at least one pad; and

,

forming a coating (56) over the at least one peak and the upper surface of the lower portion of the at least one pad, the coating (56) consisting of the same at least one eutectic alloy component comprising the upper portion of the at least one pad.

10. The method of any one of claims 1-3, wherein forming the at least one sharp peak (50, 58) is characterized by:

forming a lower portion (42, 44, 46, 48) of the at least one pad (12, 14, 20, 22), the lower portion comprising a metal or a semiconductor;

forming a first coating (60) on an upper surface of the lower portion of the at least one pad, the first coating consisting of the same at least one eutectic alloy component comprising the upper portion of the at least one pad;

forming the at least one peak (50, 58) on an upper surface of the first coating (60); and

,

forming a second coating (62) over the at least one peak (50, 58) and the upper surface of the first coating (60), the second coating consisting of the same at least one eutectic alloy component comprising the upper portion of the at least one pad.

11. The method of claim 2, further characterized by molding a monolithic body (122) of a dielectric plastic over the die (12) and at least a portion of the interconnective substrate (18), thereby hermetically sealing the die.

12. The method of claim 2, further characterized by placing a lid (124) over the die (12) and forming a continuous seal around a periphery of the die and between a peripheral portion of the lid and the interconnective substrate (18), thereby hermetically sealing the die.

13. The method of any one of claims 1-3, wherein the second substrate (18) has a second surface opposite to the first surface thereof, the second surface having a electrically conductive land (30) thereon, and further characterized by forming an electrically conductive, hermetically sealed via (32) through the second substrate connecting the second pad (16) to the land.

14. The method of claim 13, wherein the land (30) and the via (32) are laterally offset from the second pad (16).

15. A semiconductor package (10) made in accordance with any one of the methods of claims 2, 3, 11, or 12.

16. A semiconductor package (10) made in accordance with the method of claim 14.