Method and system for capturing and bypassing memory transactions in a hub-based memory system
First Claim
1. A memory hub, comprising:
- a reception interface operable to receive data words and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain;
a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on an output; and
local control circuitry coupled to the output of the reception interface to receive the groups of data words, the local control circuitry operable to develop memory requests corresponding to the groups of data words.
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Abstract
A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock signal in a second time domain. A transmission interface is coupled to the reception interface to receive the captured data words and captures the data words in response to a third clock signal in the first time domain. This interface provides the captured data words on an output. Local control circuitry is coupled to the output of the reception interface to receive the groups of data words and develops memory requests corresponding to the groups of data words. The first clock domain is defined by clock signals having frequencies higher than frequencies of clock signals in the second clock domain.
148 Citations
47 Claims
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1. A memory hub, comprising:
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a reception interface operable to receive data words and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain;
a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on an output; and
local control circuitry coupled to the output of the reception interface to receive the groups of data words, the local control circuitry operable to develop memory requests corresponding to the groups of data words. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a reception interface operable to receive data words and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain;
a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on an output; and
local control circuitry coupled to the output of the reception interface to receive the groups of data words and also coupled to the memory devices, the local control circuitry operable to apply memory requests corresponding to the groups of memory devices responsive to at least some of the memory requests. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a physical reception port adapted to receive data words;
a bypass path coupled to the physical reception port;
a physical transmission port coupled to the bypass path; and
local control circuitry coupled to the physical reception port and to the plurality of memory devices. - View Dependent Claims (15, 16, 17, 18)
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19. A memory system, comprising:
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a system controller;
a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;
a plurality of memory devices;
a reception interface operable to receive data words from the corresponding high-speed communications link and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain;
a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on the corresponding high-speed communications link; and
local control circuitry coupled to the output of the reception interface to receive the groups of data words and also coupled to the memory devices, the local control circuitry operable to apply memory requests corresponding to the groups of data words to the memory devices to access memory cells in at least one of the memory devices responsive to at least some of the memory requests. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A computer system, comprising:
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a central processing unit (“
CPU”
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a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;
a plurality of memory devices;
a reception interface operable to receive data words from the corresponding high-speed communications link and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain;
a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on the corresponding high-speed communications link; and
local control circuitry coupled to the output of the reception interface to receive the groups of data words and also coupled to the memory devices, the local control circuitry operable to apply memory requests corresponding to the groups of data words to the memory devices to access memory cells in at least one of the memory devices responsive to at least some of the memory requests. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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37. A method of processing downstream memory requests in a memory system including a plurality of memory hubs connected in a serial configuration, the method comprising:
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receiving a data word at each memory hub;
latching each received data word in the memory hub responsive to a first clock signal in a first clock domain;
forwarding each latched data word to the next downstream memory hub responsive to a second clock signal in the first time domain; and
processing in each memory hub the latched data word responsive to a third clock signal in a second time domain, the second clock domain being defined by clock signals having rates lower than rates of clock signals in the first time domain. - View Dependent Claims (38, 39, 40, 41, 42)
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43. A method of processing downstream memory requests in a memory system including a plurality of memory hubs, the memory hubs being coupled in a daisy-chain configuration and the method comprising:
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capturing downstream data words in each memory hub in a first clock domain;
bypassing each memory hub in the first clock domain to provide each captured downstream data word to a next adjacent downstream memory hub; and
processing in each memory hub the captured data word in a second clock domain being defined by clock signals having frequencies less than the frequencies of clock signals in the first clock domain. - View Dependent Claims (44, 45, 46, 47)
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Specification