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Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture

  • US 20050044327A1
  • Filed: 08/19/2003
  • Published: 02/24/2005
  • Est. Priority Date: 08/19/2003
  • Status: Active Grant
First Claim
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1. A method of controlling independent and asynchronous access to a memory by a plurality of processes, the method comprising:

  • while providing for independent and asynchronous performance of a memory read process of the plurality of processes, independently and asynchronously performing a memory write process of the plurality of processes, wherein the memory write process comprises;

    obtaining a first copy of a memory full indicator;

    obtaining a copy of a read index, the read index copy indicating a read element position in the memory;

    when the first copy of the memory full indicator indicates that the memory is not full, determining an available write count from the read index copy and a write index, the write index indicating a write element position in the memory;

    beginning at the write element position, writing an amount of data corresponding to the available write count; and

    updating the write index to indicate a next write element position based upon the amount of data written.

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