Split computer architecture

• US 20050044439A1
• Filed: 09/10/2004
• Published: 02/24/2005
• Est. Priority Date: 10/30/1998
• Status: Active Grant

• Current Assignee: Vertiv IT Systems, Inc. (Vertiv Holdings Co.)
• Original Assignee: Avocent Corporation (Vertiv Holdings Co.)
• Inventors: Thomas, Christopher L., O'Bryant, Greg, Luterman, Greg, Asprey, Robert R., Choun, Jeffrey E., Shatas, Remigius G.
• Granted Patent: US 7,320,043 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H04L 67/01 Protocols
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Claims

1-41. -41. (cancelled)

42. A system for communicating digital computer data over extended distances comprising:

a processor coupled to a first communication link and generating digital data for communication on the first communication link, wherein the data is communicated according to a standard digital communication format, and wherein the data generated by the processor includes information providing video data for use by a video monitor;

a first logic device receiving the digital data generated by the processor and communicated on the first link, the first logic device converting the received digital data into a second digital communication format different from the standard digital communication format, and coupling the converted data to a second communication link different from the first communication link;

a second logic device coupled to the second communication link and receiving the converted data from the first logic device, the second logic device converting the data from the second link into a third digital communication format and coupling the data in the third digital communication format to a third communication link different from the first and second communication links;

a video processing circuit coupled to the third communication link and receiving therefrom at least the information providing video data generated by the processor, the video processing circuit providing the video data as a format suitable for use by the video monitor and transmitting the video data to the video monitor.

43. A system for communicating digital computer data over extended distances according to claim 42, wherein the processor is a microprocessor.

44. A system for communicating digital computer data over extended distances according to claim 42, wherein the standard digital communication format is a PCI data format.

45. A system for communicating digital computer data over extended distances according to claim 42, wherein the first bus is a PCI bus.

46. A system for communicating digital computer data over extended distances according to claim 42, wherein the second digital communication format is a proprietary, non-standard digital format.

47. A system for communicating digital computer data over extended distances according to claim 42, wherein the second digital communication format is a serial data format.

48. A system for communicating digital computer data over extended distances according to claim 42, wherein the second digital communication format is a packet-based communication format.

49. A system for communicating digital computer data over extended distances according to claim 42, wherein the third digital communication format is the same as the standard digital communication format.

50. A system for communicating digital computer data over extended distances according to claim 42, wherein the data generated by the processor includes video data for use by a video monitor.

51. A system for communicating digital computer data over extended distances according to claim 42, wherein the third digital communication format is a PCI data format.

52. A system for communicating digital computer data over extended distances according to claim 42, wherein the first and third communication links comprise first and second digital communication buses.

53. A system for communicating digital computer data over extended distances according to claim 52, wherein the first and second digital communication buses are separated by at least one clock domain barrier.

54. A system for communicating digital computer data over extended distances according to claim 42, wherein the second logic device receives digital data from a keyboard and a mouse, the second logic device converting the keyboard and mouse data into a format suitable for transmission on the second communication link, and coupling the reformatted keyboard and mouse data onto the second communication link.

55. A system for communicating digital computer data over extended distances according to claim 42, wherein the second communication link is a twisted pair medium.

56. A computer communication system comprising:

a computer processor on a host system;

a video controller on a remote system located remotely from the host system and separated from the remote system by a twisted pair medium,

wherein the twisted pair medium provides a communication path for the processor to provide video information to the video controller to produce video monitor signals at the host system.