Integrated circuit with a MOS capacitor

• US 20050045934A1
• Filed: 09/28/2004
• Published: 03/03/2005
• Est. Priority Date: 11/05/2001
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Beasom, James D.
• Granted Patent: US 7,042,064 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 27/0658 Vertical bipolar transistor in combination with resistors or capacitors
• CPC Class Codes: H01L 27/067 Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0811 MIS diodes

Abstract

The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

Claims

1. An integrated circuit comprising:

a substrate having a plurality of isolation islands, wherein at least one isolation island has a semiconductor device formed therein;

a layer of oxide formed and patterned on a surface of the substrate;

a layer of dielectric formed overlaying the layer of oxide and exposed surface areas of the substrate, the layer of dielectric having a dielectric constant that is higher than the dielectric constant of the layer of oxide, wherein the dielectric layer is used as an implant screen in implanting dopants into respective isolation islands to form devices regions; and

at least one capacitor formed in one of the isolated island in the substrate, each capacitor using the layer of dielectric as a capacitor dielectric, each capacitor dielectric is positioned between a top plate and a bottom plate of an associated capacitor.

2. The integrated circuit of claim 1, further comprising:

the layer of dielectric and the layer of oxide having anisotropic device openings to expose device regions in the substrate, wherein the device openings are formed by a dry etch.

3. The integrated circuit of claim 2, wherein the dry etch used is a reactive ion etch.

4. The method of claim 1, wherein the layer of dielectric is a layer of nitride.

5. The method of claim 4, wherein the nitride layer is formed by low pressure chemical vapor deposition.

6. An integrated circuit comprising:

a substrate of having a plurality of isolation islands, wherein at least one isolation island has a semiconductor device formed therein;

a layer of oxide formed and patterned on a surface of the substrate;

a layer of dielectric formed overlaying the layer of oxide and exposed surface areas of the substrate, wherein the layer of dielectric has a dielectric constant that is higher than the dielectric constant of the layer of oxide;

the layer of dielectric and the layer of oxide having anisotropic device openings to expose device regions in the substrate, wherein the device openings are formed by a dry etch; and

at least one capacitor formed in one of the isolated islands in the substrate, each capacitor using the layer of dielectric as a capacitor dielectric, each capacitor dielectric is positioned between a top plate and a bottom plate of an associated capacitor.

7. The integrated circuit of claim 6, wherein the dielectric layer is used an implant screen in implanting dopants into the respective isolation islands to form the device regions.

8. The integrated circuit of claim 6, wherein the dry etch used is a reactive ion etch.

9. The method of claim 6, wherein the layer of dielectric is a layer of nitride.

10. The method of claim 9, wherein the nitride layer is formed by low pressure chemical vapor deposition.

11. An integrated circuit comprising:

a substrate having a surface and a plurality of isolation islands;

one or more semiconductor devices, each semiconductor device is formed in an associated isolation island, some of the semiconductor devices having device regions formed adjacent the surface of the substrate;

an oxide layer formed and patterned on the surface of the substrate;

a dielectric layer overlaying the patterned oxide layer and exposed surface areas of the substrate, wherein the layer of dielectric has a dielectric constant that is higher than the dielectric constant of the layer of oxide;

the oxide and dielectric layers over select device regions having contact openings with generally vertical side walls with respect to the surface of the substrate; and

at least one capacitor formed in one of the isolation islands, the capacitor having a capacitor dielectric that is formed from a portion of the dielectric layer.

12. The integrated circuit of claim 11, further comprising:

a metal contact region formed in each contact opening to provide a contact to the associated device region.

13. The integrated circuit of claim 11, wherein one of the at least one capacitor, further comprising:

a bottom plate formed in the substrate; and

a top plate overlaying the dielectric layer, wherein the dielectric layer positioned between the top plate and the bottom plate is the capacitor dielectric.

14. The integrated circuit of claim 11, wherein the layer of dielectric is a layer of nitride.

15. The integrated circuit of claim 11, wherein a portion of the dielectric layer has a contact opening to the bottom plate.

16. The integrated circuit of claim 11, further comprising:

a bottom plate contact region formed in the contact opening to the bottom plate.

17. The integrated circuit of claim 11, wherein one of the semiconductor devices in an isolation island is a transistor, further comprising:

a base region formed in the isolation island adjacent the surface of the substrate;

a emitter formed in the base region adjacent the surface of the substrate; and

a collector contact formed in the isolation island adjacent a surface of the substrate.

18. The integrated circuit of claim 17, wherein a portion of the dielectric and oxide layers covering the base region has a contact opening that extends to the base region.