THIN CHANNEL FET WITH RECESSED SOURCE/DRAINS AND EXTENSIONS

• US 20050045947A1
• Filed: 08/26/2003
• Published: 03/03/2005
• Est. Priority Date: 08/26/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Oldiges, Philip J., Wang, Xinlin, Chen, Huajie, Doris, Bruce B., Zhu, Huilong
• Granted Patent: US 6,924,517 B2
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.

Claims

1. A field effect transistor (FET) comprising:

a thin channel having a first thickness;

a gate disposed above said thin channel;

a source/drain region in a recess at each end of said thin channel and substantially thicker than said thin channel; and

a source/drain extension between said thin channel and a corresponding said source/drain region, each said source/drain extension and said corresponding source/drain region being aligned to said gate and said thin channel.

2. A FET as in claim 1, wherein said recess extends under said gate at said each end.

3. A FET as in claim 1, wherein said recess partially extends under said gate at said each end.

4. A FET as in claim 1, wherein an upper surface of each said source/drain region is substantially coplanar with an upper surface of said thin channel.

5. A FET as in claim 1, wherein said thin channel is a semiconductor material selected from a group consisting of silicon (Si), Germanium (Ge), SiGe and strained silicon (SSi).

6. A FET as in claim 5, wherein said thin channel is strained silicon.

7. A FET as in claim 5, wherein said gate is made from a material comprising polysilicon.

8. A FET as in claim 5, wherein said gate is made from a material comprising a silicide.

9. A FET as in claim 1, wherein said thin channel is <

15 nm thick.

10. A FET as in claim 9, wherein said thin channel is 10 nm thick.

11. A FET as in claim 9, wherein said thin channel is <

40 nm long.

12. A FET as in claim 11, wherein said thin channel is 30 nm long.

13. A FET as in claim 9, wherein a lower surface of said recess is >

5 nm below said thin channel.

14. A FET as in claim 13, wherein said lower surface is 40 nm below said thin channel.

15. A FET as in claim 1, wherein said FET is disposed on an insulating layer and said insulating layer is disposed on a semiconductor substrate.

16. A FET as in claim 15, wherein said semiconductor substrate comprises a silicon substrate.

17. A FET as in claim 15, wherein said semiconductor substrate comprises a strained silicon/silicon germanium (SSi/SiGe) substrate.

18. An integrated circuit (IC) on a silicon on insulator (SOI) chip, said IC including a plurality of field effect transistors (FETs) disposed on an insulating layer, said insulating layer being on a semiconductor substrate, each of said FETs comprising:

a thin channel, said thin channel being a thin semiconductor layer and having a first thickness;

a gate disposed above said thin channel;

a source/drain region in a recess at each end of said thin channel and substantially thicker than said thin channel; and

a source/drain extension between said thin channel and a corresponding said source/drain region, each said source/drain extension and said corresponding source/drain region being aligned to said gate and said thin channel.

19. An IC as in claim 18, wherein each said recess extends under a corresponding said gate at said either end.

20. An IC as in claim 18, wherein each said recess partially extends under a corresponding said gate at said either end.

21. An IC as in claim 18, wherein said thin semiconductor layer is a layer of material selected from a group consisting of silicon (Si), Germanium (Ge), SiGe and strained silicon.

22. An IC as in claim 21, wherein said thin channel is silicon and said gate is polysilicon.

23. An IC as in claim 22, wherein said thin channel is strained silicon.

24. An IC as in claim 22, wherein said thin channel is <

15 nm thick.

25. An IC as in claim 24, wherein a lower surface of each said recess is >

5 nm below said thin channel.

26. An IC as in claim 25, wherein said thin channel is <

40 nm long.

27. An IC as in claim 26, wherein said semiconductor substrate is a silicon substrate.

28. An IC as in claim 27, wherein said semiconductor substrate is a strained silicon/silicon germanium (SSi/SiGe) substrate.

29. A method of forming an integrated circuit (1C), said method comprising the steps of:

a) defining device regions on a silicon on insulator (SOI) wafer;

b) defining source/drain areas at opposite sides of a gate in each of said device regions;

c) undercutting source/drain areas; and

d) filling undercut said source/drain areas with silicon, filled said undercut forming source/drain regions and extensions, a device channel being defined beneath each said gate self aligned to pairs of said source/drain regions and extensions.

30. A method of forming an IC as in claim 29, wherein the SOI wafer is a bonded SOI wafer having an ultra-thin silicon layer and a semiconductor substrate, said ultra-thin silicon layer being <

10 nm thick, the step (a) of defining device regions comprising the steps of;

i) forming gates on said ultra-thin silicon layer;

ii) forming trenches around device areas, said trenches being formed through said ultra-thin layer to said semiconductor substrate; and

iii) filling said trenches with an insulating material.

31. A method of forming an IC as in claim 30, wherein the step (b) of defining said source drain areas comprises forming a void between said ultra-thin silicon layer and said semiconductor substrate.

32. A method of forming an IC as in claim 31, wherein the SOI wafer further includes a sacrificial layer between said ultra-thin silicon layer and said semiconductor substrate and the step (a) of defining device regions further comprises the step of:

iv) implanting a dopant into said sacrificial layer.

33. A method of forming an IC as in claim 32, wherein said gates block said dopant implanted in implanting step (a)(iv), undoped portions of said sacrificial layer remaining beneath said gates.

34. A method of forming an IC as in claim 33, wherein the SOI wafer further includes an insulating layer between said sacrificial layer and said semiconductor substrate and forming said void in step (b) comprises the steps of:

i) opening orifices through said ultra-thin silicon layer to said semiconductor substrate at each end of each of said devices regions;

ii) removing portions of said insulating layer in said device areas between said orifices; and

iii) removing said undoped portions of said sacrificial layer, remaining doped portions of said sacrificial layer defining said source/drain areas.

35. A method of forming an IC as in claim 34, wherein the step (c) of undercutting the source/drain areas comprises the steps of:

i) filling said void with an insulating material, said insulating material at least partially filling said orifices such that at least the bottom of said remaining doped portions is below an upper surface of said fill insulating material;

ii) removing remaining said doped portions; and

iii) exposing an underside of said ultra-thin silicon layer above removed said doped portions.

36. A method of forming an IC as in claim 35, wherein said insulating layer fills said orifices and the step (c)(i) further comprises etching said insulating material back.

37. A method of forming an IC as in claim 36, wherein remaining said doped portions are doped with a first dopant type and the step (c)(ii) of removing remaining said doped portions comprises:

A) implanting a second dopant type into remaining said doped portions;

B) annealing said SOI wafer, remaining said doped portions changing semiconductor type to said second type; and

C) selectively etching with an etchant selective to said second type.

38. A method of forming an IC as in claim 37, wherein the step (d) of filling said undercut source/drain and extension areas comprises growing silicon epitaxially in said undercut source/drain areas, said epitaxially grown silicon growing from said ultra-thin silicon layer and filling said undercut source/drain areas, a recessed extension and source/drain being formed by said epitaxially grown silicon and said ultra-thin silicon layer at each end of said self aligned channel.