Integrated circuit device having input/output electrostatic discharge protection cell equipment with electrostatic discharge protection element and power clamp
First Claim
1. An integrated circuit device having an I/O ESD (input/output electrostatic discharge) protection cell, wherein the I/O ESD protection cell comprises:
- a power supply voltage (VDD ) ESD protection element connected between an I/O pad and a VDD line;
a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line; and
a power clamp element connected between the VDD line and the VSS line, wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.
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Accused Products
Abstract
There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.
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Citations
43 Claims
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1. An integrated circuit device having an I/O ESD (input/output electrostatic discharge) protection cell,
wherein the I/O ESD protection cell comprises: -
a power supply voltage (VDD ) ESD protection element connected between an I/O pad and a VDD line;
a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line; and
a power clamp element connected between the VDD line and the VSS line, wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit device having an I/O ESD protection cell, wherein the I/O ESD protection cell comprises:
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a power supply voltage (VDD ) ESD protection element formed within a second conductivity type well in a first conductivity type substrate and comprising a first conductivity type active region connected to an I/O pad and a second conductivity type active region connected to a VDD line;
a power clamp element formed within the second conductivity type well in the first conductivity type substrate and comprising the second conductivity type active region connected to the VDD line and the first conductivity type active region connected to a ground voltage (VSS) line; and
a VSS ESD protection element formed within a first conductivity type well in the first conductivity type substrate and comprising the first conductivity type active region connected to the VSS line and the second conductivity type active region connected to the I/O pad. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. An integrated circuit device having an I/O ESD protection cell, wherein the I/O ESD protection cell comprises:
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a power supply voltage (VDD ) ESD protection element formed within a second conductivity type well in a first conductivity type substrate and comprising a first conductivity type active region connected to an I/O pad and a second conductivity type active region connected to a VDD line;
a power clamp element formed within a first conductivity type well in the first conductivity type substrate and comprising the second conductivity type active region connected to the VDD line and the first conductivity type active region connected to a ground voltage (VSS) line; and
a VSS ESD protection element formed within the first conductivity type well in the first conductivity type substrate and comprising the first conductivity type active region connected to the VSS line and the second conductivity type active region connected to the I/O pad. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. An integrated circuit device having an I/O ESD protection cell, wherein the I/O ESD protection cell comprises:
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a power supply voltage (VDD ) ESD protection element comprising first conductivity type active regions and a first gate, wherein the first conductivity type active regions are formed within a second conductivity type well in a first conductivity type substrate and separated from one another to define a first channel region, at least one of the first conductivity type active regions being connected to an I/O pad and the other being connected to a VDD line, and the first gate is formed on the first channel region;
a power clamp element comprising second conductivity type active regions and a second gate, wherein the second conductivity type active regions are formed within a first conductivity type well in the first conductivity type substrate and separated from one another to define a second channel region, at least one of the second conductivity type active regions being connected to the VDD line and the other being connected to a VSS line, and the second gate being formed on the second channel region; and
a VSS ESD protection element comprising the second conductivity type active regions and a third gate, wherein the second conductivity type active regions are formed within the first conductivity type well in the first conductivity type substrate and separated from one another to define a third channel region, at least one of the second conductivity type active regions being connected to an I/O pad and the other being connected to the VSS line, and the third gate being formed on the third channel region. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. An integrated circuit device having an I/O ESD protection cell, wherein the I/O ESD protection cell comprises:
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a power supply voltage (VDD ) ESD protection element comprising first conductivity type active regions and a first gate, wherein the first conductivity type active regions are formed within a second conductivity type well in a first conductivity type substrate and separated from one another to define a first channel region, at least one of the first conductivity type active regions being connected to an I/O pad and the other being connected to a VDD line, and the first gate is formed on the first channel region;
a power clamp element comprising the first conductivity type active regions and a second gate, wherein the first conductivity type active regions are formed within the second conductivity type well in the first conductivity type substrate and separated from one another to define the second channel region, at least one of the first conductivity type active regions being connected to the VDD line and the other being connected to the VSS line, and the second gate being formed on the second channel region; and
a VSS ESD protection element comprising the second conductivity type active regions and a third gate, wherein the second conductivity type active regions are formed within the first conductivity type well in the first conductivity type substrate and separated from one another to define a third channel region, at least one of the second conductivity type active regions being connected to an I/O pad and the other being connected to the VSS line, and the third gate being formed on the third channel region. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43)
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Specification