Insulated gate transistor incorporating diode

• US 20050045960A1
• Filed: 08/13/2004
• Published: 03/03/2005
• Est. Priority Date: 08/27/2003
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Granted Patent: US 7,154,145 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A p-type base layer shaped like a well is formed for each of IGBT cells, and a p⁺-type collector layer and an n⁺-type cathode layer are formed on a surface opposite to a surface on which the p-type base layer is formed so as to be situated just below the p-type base layer. The p-type base layer of each of the IGBT cells includes a flat region including an emitter region and a bottom surface penetrated by a main trench, and first and second side diffusion regions between which the flat region is interposed. The first side diffusion region is situated just above the n⁺-type cathode layer and each of the bottom surfaces of the side diffusion regions forms a parabola-shaped smooth curve in longitudinal section. By replacing the p⁺-type collector layer with the n⁺-type cathode layer, it is possible to apply features of the above structure to a power MOSFET.

Claims

1. An insulated gate transistor comprising:

a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface;

a first semiconductor layer of a second conductivity type shaped like a well which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first side diffusion region, a second side diffusion region facing said first side diffusion region and a flat region which is interposed between said first side diffusion region and said second side diffusion region and comprises a bottom surface forming a substantially flat surface substantially parallel to said first main surface;

a main trench passing from said first main surface through a bottom surface of said first semiconductor layer, said main trench comprising a bottom portion situated just below said first semiconductor layer in said semiconductor substrate;

an insulating film formed on said main trench so that each of said bottom portion and a side surface of said main trench is entirely covered with said insulating film;

a control gate formed over said insulating film and filled into said main trench;

a second semiconductor layer of said first conductivity type extending from said first main surface toward an interior of said flat region of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and are vertically interposed between said top surface and said bottom surface of said second semiconductor layer;

a first main electrode formed on said top surface of said second semiconductor layer and said first side diffusion region of said first semiconductor layer;

a fourth semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate; and

a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said fourth semiconductor layer, wherein

said first side surface of said second semiconductor layer is joined to said side surface of said main trench,

said first side diffusion region is situated just above said fourth semiconductor layer,

a depth of said first side diffusion region between said first main surface and a bottom surface of said first side diffusion region continuously and smoothly changes while gradually decreasing from a position of the largest depth as a distance to a joint on said first main surface between said first main electrode and a top surface of said first side diffusion region decreases, and

a depth of said second side diffusion region between said first main surface and a bottom surface of said second side diffusion region continuously and smoothly changes while gradually decreasing from a position of the largest depth as a distance to a joint on said first main surface between said first main electrode and a top surface of said second side diffusion region decreases.

2. The insulated gate transistor according to claim 1, further comprising:

a first auxiliary trench passing from said first main surface through said bottom surface of said first side diffusion region and comprising a bottom portion situated below said first side diffusion region in said semiconductor substrate.

3. The insulated gate transistor according to claim 2, wherein

said first auxiliary trench passes through only a portion of said bottom surface of said first side diffusion region, said portion including an intersection between said top surface of said first side diffusion region and said bottom surface of said first side diffusion region which is provided without said first auxiliary trench, and a region near said intersection, and

said bottom portion of said first auxiliary trench is situated just below said intersection in said semiconductor substrate.

4. The insulated gate transistor according to claim 2, wherein

said first auxiliary trench passes through only a portion of said bottom surface of said first side diffusion region, said portion including a region near a joint between said bottom surface of said first side diffusion region and said bottom surface of said flat region, and

said bottom surface of said first side diffusion region extends to meet said first main surface.

5. The insulated gate transistor according to claim 2, further comprising:

a second auxiliary trench passing from said first main surface through said bottom surface of said second side diffusion region and comprising a bottom portion situated below said second side diffusion region in said semiconductor substrate.

6. The insulated gate transistor according to claim 5, wherein

said second auxiliary trench passes through only a portion of said bottom surface of said second side diffusion region, said portion including an intersection between said top surface of said second side diffusion region and said bottom surface of said second side diffusion region which is provided without said second auxiliary trench, and a region near said intersection, and

said second auxiliary trench comprises a bottom surface situated just below said intersection in said semiconductor substrate

7. The insulated gate transistor according to claim 5, wherein

said second auxiliary trench passes through only a portion of said bottom surface of said second side diffusion region, said portion including a region near a joint between said bottom surface of said second side diffusion region and said bottom surface of said flat region, and

said bottom surface of said second side diffusion region extends to meet said first main surface.

8. The insulated gate transistor according to claim 1, wherein

said main trench forms a first main trench interposed between said flat region and said first side diffusion region,

said insulated gate transistor further comprises:

a second main trench which passes from said first main surface through said bottom surface of said first semiconductor layer and comprises a bottom portion situated just below said first semiconductor layer in said semiconductor substrate and a side surface interposed between said flat region and said second side diffusion region.

9. The insulated gate transistor according to claim 8, further comprising:

a first auxiliary trench passing from said first main surface through said bottom surface of said first side diffusion region and comprising a bottom portion situated below said first side diffusion region in said semiconductor substrate.

10. The insulated gate transistor according to claim 9, further comprising:

a second auxiliary trench passing from said first main surface through said bottom surface of said second side diffusion region and comprising a bottom portion situated below said second side diffusion region in said semiconductor substrate.

11. The insulated gate transistor according to claim 1, further comprising:

a well layer of said second conductivity type extending from said main surface toward said interior of said semiconductor substrate and facing said first side diffusion region, wherein

said first main electrode is formed also on an inter-well region in said first main surface, said inter-well region being interposed between a joint between a bottom surface of said well layer and said first main surface and a joint between said bottom surface of said first side diffusion region and said first main surface, and

a thin film forming a Schottky junction is provided between a portion of said first main electrode situated immediately on said inter-well region and a portion of said semiconductor substrate situated just below said inter-well region.

12. The insulated gate transistor according to claim 1, further comprising:

a well layer of said second conductivity type extending from said main surface toward said interior of said semiconductor substrate and facing said first side diffusion region, wherein

said first main electrode is formed also on an inter-well region in said first main surface, said inter-well region being interposed between a joint between a bottom surface of said well layer and said first main surface and a joint between said bottom surface of said first side diffusion region and said first main surface, and

a thin film of said second conductivity type is provided between a portion of said first main electrode situated immediately on said inter-well region and a portion of said semiconductor substrate situated just below said inter-well region, said thin film comprising a lower impurity concentration than that of said first semiconductor layer and said well layer and comprising a smaller thickness than that of said first semiconductor layer, said well layer and said portion of said first main electrode situated immediately on said inter-well region.

13. The insulated gate transistor according to claim 11, further comprising:

an auxiliary trench passing from said inter-well region in said first main surface and comprising a bottom portion in a portion of said semiconductor substrate situated just below said thin film.

14. The insulated gate transistor according to claim 12, further comprising:

an auxiliary trench passing from said inter-well region in said first main surface and comprising a bottom portion in a portion of said semiconductor substrate situated just below said thin film.

15. The insulated gate transistor according to claim 11, further comprising:

a plurality of auxiliary trenches each passing from said inter-well region in said first main surface and comprising a bottom portion in a portion of said semiconductor substrate situated below said thin film.

16. The insulated gate transistor according to claim 15, wherein

a distance between respective central axes of every two adjacent ones of said plurality of auxiliary trenches is smaller than a distance between respective central axes of one of said plurality of auxiliary trenches situated closest to said first semiconductor layer and said main trench.

17. The insulated gate transistor according to claim 12, further comprising:

a plurality of auxiliary trenches each passing from said inter-well region in said first main surface and comprising a bottom portion in a portion of said semiconductor substrate situated below said thin film in said inter-well region.

18. The insulated gate transistor according to claim 17, wherein

a distance between respective central axes of every two adjacent ones of said plurality of auxiliary trenches is smaller than a distance between respective central axes of one of said plurality of auxiliary trenches situated closest to said first semiconductor layer and said main trench.

19. The insulated gate transistor according to claim 11, wherein

said first side diffusion region comprises:

a first auxiliary trench passing from said first main surface through said first side diffusion region and reaching said semiconductor substrate;

a first inactivated region of said second conductivity type interposed between said side surface of said main trench and a side surface of said first auxiliary trench;

a first interlayer insulating film formed to completely cover a top surface of said first inactivated region which is included in said first main surface; and

a first main side diffusion region of said second conductivity type comprising a bottom surface situated at a depth which gradually decreases as a distance from said side surface of said first auxiliary trench increases and a distance to said first main surface decreases.

20. The insulated gate transistor according to claim 12, wherein

said first side diffusion region comprises:

a first auxiliary trench passing from said first main surface through said first side diffusion region and reaching said semiconductor substrate;

a first inactivated region of said second conductivity type interposed between said side surface of said main trench and a side surface of said first auxiliary trench;

a first interlayer insulating film formed to completely cover a top surface of said first inactivated region which is included in said first main surface; and

a first main side diffusion region of said second conductivity type comprising a bottom surface situated at a depth which gradually decreases as a distance from said side surface of said first auxiliary trench increases and a distance to said first main surface decreases.

21. The insulated gate transistor according to claim 8, wherein

a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface are alternately arranged to form a striped pattern.

22. The insulated gate transistor according to claim 21, wherein

said MOS structure zone is smaller in area than said diode zone.

23. The insulated gate transistor according to claim 8, wherein

one of a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface is surrounded by the other of said MOS structure zone and said diode zone.

24. The insulated gate transistor according to claim 9, wherein

a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface are alternately arranged to form a striped pattern.

25. The insulated gate transistor according to claim 24, wherein

said MOS structure zone is smaller in area than said diode zone.

26. The insulated gate transistor according to claim 9, wherein

one of a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface is surrounded by the other of said MOS structure zone and said diode zone.

27. The insulated gate transistor according to claim 10, wherein

a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface are alternately arranged to form a striped pattern.

28. The insulated gate transistor according to claim 27, wherein

said MOS structure zone is smaller in area than said diode zone.

29. The insulated gate transistor according to claim 10, wherein

one of a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface is surrounded by the other of said MOS structure zone and said diode zone.

30. The insulated gate transistor according to claim 1, further comprising:

a third semiconductor layer of said second conductivity type which extends from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate, is adjacent to said fourth semiconductor layer, and is electrically connected to said second main electrode.

31. An inverter circuit comprising:

the insulated gate transistor according to claim 30 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

32. The insulated gate transistor according to claim 1, wherein

said fourth semiconductor layer extends from all portions of said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate.

33. An inverter circuit comprising:

the insulated gate transistor according to claim 32 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

34. An insulated gate transistor comprising:

a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface;

a first semiconductor layer of a second conductivity type which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first bottom surface forming a substantially flat surface substantially parallel to said first main surface;

a fifth semiconductor layer of said second conductivity type which extends from said first main surface of said semiconductor substrate toward said interior of said semiconductor substrate and comprises a second bottom surface which forms a substantially flat surface substantially parallel to said first main surface and is situated at a depth smaller than a depth at which said first bottom surface is situated;

a main trench passing from said first main surface toward said interior of said semiconductor substrate to separate said first semiconductor layer and said fifth semiconductor layer from each other, said main trench comprising a bottom portion situated at a depth greater than said depth at which said first bottom surface is situated;

an insulating film formed on said main trench so that each of said bottom portion and a side surface of said main trench is entirely covered with said insulating film;

a control electrode formed over said insulating film and filled into said main trench;

a second semiconductor layer of said first conductivity type which extends from said first main surface toward an interior of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and vertically interposed between said top surface and said bottom surface;

a first main electrode formed on said top surface of said second semiconductor layer and a top surface of said fifth semiconductor layer;

a fourth semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate; and

a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said fourth semiconductor layer, wherein

said first side surface of said second semiconductor layer is joined to said side surface of said main trench,

said second bottom surface of said fifth semiconductor layer faces said fourth semiconductor layer with said semiconductor substrate interposed therebetween, and

an impurity concentration of said fifth semiconductor layer is lower than that of said first semiconductor layer.

35. The insulated gate transistor according to claim 34, wherein

a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface are alternately arranged to form a striped pattern.

36. The insulated gate transistor according to claim 35, wherein

said MOS structure zone is smaller in area than said diode zone.

37. The insulated gate transistor according to claim 34, wherein

one of a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface is surrounded by the other of said MOS structure zone and said diode zone.

38. The insulated gate transistor according to claim 34, further comprising:

a third semiconductor layer of said second conductivity type which extends from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate, is adjacent to said fourth semiconductor layer, and is electrically connected to said second main electrode.

39. An inverter circuit comprising:

the insulated gate transistor according to claim 38 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

40. The insulated gate transistor according to claim 34, wherein

said fourth semiconductor layer extends from all portions of said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate.

41. An inverter circuit comprising:

the insulated gate transistor according to claim 40 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

42. An insulated gate transistor comprising:

a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface;

a first semiconductor layer of a second conductivity type shaped like a well which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first side diffusion region, a second side diffusion region facing said first side diffusion region and a flat region which is interposed between said first side diffusion region and said second side diffusion region and comprises a first bottom surface forming a substantially flat surface substantially parallel to said first main surface;

a main trench passing from said first main surface through said first semiconductor layer toward said interior of said semiconductor substrate, to separate said first side diffusion region and said flat region from each other, said main trench comprising a bottom portion situated at a depth greater than a depth at which said first bottom surface is situated;

an insulating film formed on said main trench so that each of said bottom portion and a side surface of said main trench is entirely covered with said insulating film;

a control electrode formed over said insulating film and filled into said main trench;

a second semiconductor layer of said first conductivity type extending from said first main surface toward an interior of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and are vertically interposed between said top surface and said bottom surface of said second semiconductor layer;

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and facing said first side diffusion region;

a fifth semiconductor layer of said second conductivity type extending from a region in said first main surface which is interposed between said first side diffusion region and a side diffusion region of said well layer toward said interior of said semiconductor substrate, said fifth semiconductor layer being joined to a portion of said first side diffusion region and a portion of said side diffusion region of said well layer, and comprising a second bottom surface which forms a substantially flat surface substantially parallel to said first main surface and is situated at a depth smaller than said depth at which said first bottom surface is situated;

a fourth semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate;

a first main electrode formed on said top surface of said second semiconductor layer and a top surface of said fifth semiconductor layer; and

a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said fourth semiconductor layer, wherein

said first side surface of said second semiconductor layer is joined to said side surface of said main trench,

said second bottom surface of said fifth semiconductor layer faces said fourth semiconductor layer with said semiconductor substrate interposed therebetween, and

an impurity concentration of said fifth semiconductor layer is lower than that of said first semiconductor layer.

43. The insulated gate transistor according to claim 42, wherein

a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface are alternately arranged to form a striped pattern.

44. The insulated gate transistor according to claim 43, wherein

said MOS structure zone is smaller in area than said diode zone.

45. The insulated gate transistor according to claim 42, wherein

one of a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface is surrounded by the other of said MOS structure zone and said diode zone.

46. The insulated gate transistor according to claim 42, further comprising:

a third semiconductor layer of said second conductivity type which extends from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate, is adjacent to said fourth semiconductor layer, and is electrically connected to said second main electrode.

47. An inverter circuit comprising:

the insulated gate transistor according to claim 46 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

48. The insulated gate transistor according to claim 42, wherein

said fourth semiconductor layer extends from all portions of said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate.

49. An inverter circuit comprising:

the insulated gate transistor according to claim 48 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

50. An insulated gate transistor comprising:

a semiconductor substrate of a first conductivity type comprising a first main surface and a second main surface;

a first semiconductor layer of a second conductivity type which extends from said first main surface of said semiconductor substrate toward an interior of said semiconductor substrate and comprises a first bottom surface forming a substantially flat surface substantially parallel to said first main surface;

a main trench passing from said first main surface toward said interior of said semiconductor substrate and comprising a bottom portion situated at a depth greater than a depth at which said first bottom surface is situated;

an insulating film formed on said main trench so that each of said bottom portion and a side surface of said main trench is entirely covered with said insulating film;

a control electrode formed over said insulating film and filled into said main trench;

a second semiconductor layer of said first conductivity type which extends from said first main surface toward an interior of said first semiconductor layer, said second semiconductor layer comprising a top surface included in said first main surface, a bottom surface facing said top surface, and first and second side surfaces which face each other and vertically interposed between said top surface and said bottom surface;

a sixth semiconductor layer of said first conductivity type comprising a top surface which is in face-to-face contact with said first bottom surface of said first semiconductor layer, a third bottom surface facing an interface between said top surface of said sixth semiconductor layer and said first bottom surface of said first semiconductor layer, and third and fourth side surfaces vertically interposed between said interface and said third bottom surface;

a first main electrode formed on a top surface of said first semiconductor layer and said top surface of said second semiconductor layer which are included in said first main surface;

a fourth semiconductor layer of said first conductivity type extending from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate;

a second main electrode formed on said second main surface of said semiconductor substrate and electrically connected to said fourth semiconductor layer, wherein

each of said first side surface of said second semiconductor layer, a side surface of said first semiconductor layer connected to said bottom surface of said second semiconductor layer and said third side surface of said sixth semiconductor layer is joined to said side surface of said main trench, and

an impurity concentration of said sixth semiconductor layer is higher than that of said first semiconductor layer and is lower than that of said fourth semiconductor layer.

51. The insulated gate transistor according to claim 50, further comprising:

a fifth semiconductor layer of said second conductivity type extending from said first main surface of said semiconductor substrate toward said interior of said semiconductor substrate, said fifth semiconductor layer comprising a side surface which faces each of said first side surface of said second semiconductor layer and said side surface of said first semiconductor layer with said main trench interposed therebetween, and a second bottom surface which forms a substantially flat surface substantially parallel to said first main surface and is situated at a depth smaller than a depth at which said third bottom surface is situated, and said fifth semiconductor layer being joined to said first main electrode on said first main surface, wherein

an impurity concentration of said fifth semiconductor layer is lower than that of said first semiconductor layer.

52. The insulated gate transistor according to claim 50, further comprising:

a first side diffusion region of said second conductivity type extending from said first main surface along said side surface of said main trench toward said interior of said semiconductor substrate, said first side diffusion region being separated from each of said first side surface of said second semiconductor layer, said side surface of said first semiconductor layer and said third side surface of said sixth semiconductor layer by said main trench, and comprising a bottom surface situated at a depth which gradually and smoothly increases to be smaller than said depth at which said bottom portion of said main trench is situated;

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and facing said first side diffusion region; and

a fifth semiconductor layer of said second conductivity type extending from a region in said first main surface which is interposed between said first side diffusion region and a side diffusion region of said well layer toward said interior of said semiconductor substrate, said fifth semiconductor layer being joined to a portion of said first side diffusion region and a portion of said side diffusion region of said well layer and further joined to said first main electrode on said first main surface, and said fifth semiconductor layer comprising a second bottom surface which forms a substantially flat surface substantially parallel to said first main surface and is situated at a depth smaller than a depth at which said third bottom surface is situated, wherein

an impurity concentration of said fifth semiconductor layer is lower than that of each of said first semiconductor layer and said first side diffusion region.

53. The insulated gate transistor according to claim 50, further comprising:

a first side diffusion region of said second conductivity type extending from said first main surface along said side surface of said main trench toward said interior of said semiconductor substrate, said first side diffusion region being joined to said first main electrode on said first main surface and being separated from each of said first side surface of said second semiconductor layer, said side surface of said first semiconductor layer and said third side surface of said sixth semiconductor layer by said main trench, said first side diffusion region comprising a bottom surface situated at a depth which gradually and smoothly increases to be smaller than said depth at which said bottom portion of said main trench is situated; and

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and comprising a side diffusion region facing said first side diffusion region, wherein

said bottom surface of said first side diffusion region and a bottom surface of said side diffusion region of said well layer are connected to each other on said first main surface.

54. The insulated gate transistor according to claim 50, further comprising:

a first side diffusion region of said second conductivity type extending from said first main surface along said side surface of said main trench toward said interior of said semiconductor substrate, said first side diffusion region being joined to said first main electrode on said first main surface and being separated from each of said first side surface of said second semiconductor layer, said side surface of said first semiconductor layer and said third side surface of said sixth semiconductor layer by said main trench, said first side diffusion region comprising a bottom surface situated at a depth which gradually and smoothly increases to be smaller than said depth at which said bottom portion of said main trench is situated; and

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and comprising a side diffusion region facing said first side diffusion region with said semiconductor substrate interposed therebetween, wherein

said first main electrode is formed also on an inter-well region in said first main surface, said inter-well region being interposed between a joint between a bottom surface of said side diffusion region of said well layer and said first main surface and a joint between said bottom surface of said first side diffusion region and said first main surface, and

a thin film forming a Schottky junction is provided between a portion of said first main electrode situated immediately on said inter-well region and a portion of said semiconductor substrate situated just below said inter-well region.

55. The insulated gate transistor according to claim 50, further comprising:

a first side diffusion region of said second conductivity type extending from said first main surface along said side surface of said main trench toward said interior of said semiconductor substrate, said first side diffusion region being joined to said first main electrode on said first main surface and being separated from each of said first side surface of said second semiconductor layer, said side surface of said first semiconductor layer and said third side surface of said sixth semiconductor layer by said main trench, said first side diffusion region comprising a bottom surface situated at a depth which gradually and smoothly increases to be smaller than said depth at which said bottom portion of said main trench is situated; and

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and comprising a side diffusion region facing said first side diffusion region with said semiconductor substrate interposed therebetween, wherein

said first main electrode is formed also on an inter-well region in said first main surface, said inter-well region being interposed between a joint between a bottom surface of said side diffusion region of said well layer and said first main surface and a joint between said bottom surface of said first side diffusion region and said first main surface, and

a thin film of said second conductivity type is provided between a portion of said first main electrode situated immediately on said inter-well region and a portion of said semiconductor substrate situated just below said inter-well region, said thin film comprising a lower impurity concentration than that of each of said first semiconductor layer and said well layer and comprising a smaller thickness than that of each of said first semiconductor layer, said well layer and said portion of said first main electrode situated immediately on said inter-well region.

56. The insulated gate transistor according to claim 50, further comprising:

an auxiliary trench passing from said first main surface toward said interior of said semiconductor substrate and comprising a bottom portion situated at a depth greater than a depth at which said third bottom surface is situated, said auxiliary trench being situated adjacent to said main trench;

a different insulating film formed on said auxiliary trench so that each of said bottom portion and a side surface of said auxiliary trench is entirely covered with said different insulating film;

a flat region of said second conductivity type interposed between said side surface of said main trench and said side surface of said auxiliary trench, said flat region comprising a top surface included in said first main surface of said semiconductor substrate and a fourth bottom surface situated at a depth greater than said depth at which said first bottom surface is situated and smaller than said depth at which said third bottom surface is situated;

an interlayer insulating film formed over said top surface of said flat region; and

a first side diffusion region of said second conductivity type extending from said first main surface along said side surface of said auxiliary trench toward said interior of said semiconductor substrate and facing said flat region with said auxiliary trench interposed therebetween, said first side diffusion region comprising a top surface joined to said first main electrode on said first main surface and a bottom surface situated at a depth which gradually and smoothly increases to be smaller than said depth at which said bottom portion of said auxiliary trench is situated.

57. The insulated gate transistor according to claim 56, further comprising:

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and comprising a side diffusion region facing said first side diffusion region with said semiconductor substrate interposed therebetween, wherein

said first main electrode is formed also on an inter-well region in said first main surface, said inter-well region being interposed between a joint between a bottom surface of said side diffusion region of said well layer and said first main surface and a joint between said bottom surface of said first side diffusion region and said first main surface, and

a thin film forming a Schottky junction is provided between a portion of said first main electrode situated immediately on said inter-well region and a portion of said semiconductor substrate situated just below said inter-well region.

58. The insulated gate transistor according to claim 56, further comprising:

a well layer of said second conductivity type extending from said first main surface toward said interior of said semiconductor substrate and comprising a side diffusion region facing said first side diffusion region with said semiconductor substrate interposed therebetween, wherein

said first main electrode is formed also on an inter-well region in said first main surface, said inter-well region being interposed between a joint between a bottom surface of said side diffusion region of said well layer and said first main surface and a joint between said bottom surface of said first side diffusion region and said first main surface, and

a thin film of said second conductivity type is provided between a portion of said first main electrode situated immediately on said inter-well region and a portion of said semiconductor substrate situated just below said inter-well region, said thin film comprising a lower impurity concentration than that of each of said first semiconductor layer and said well layer and comprising a smaller thickness than that of each of said first semiconductor layer, said well layer and said portion of said first main electrode situated immediately on said inter-well region.

59. The insulated gate transistor according to claim 50, wherein

a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface are alternately arranged to form a striped pattern.

60. The insulated gate transistor according to claim 59, wherein

said MOS structure zone is smaller in area than said diode zone.

61. The insulated gate transistor according to claim 50, wherein

one of a MOS structure zone corresponding to a zone occupied by a MOS structure in said first main surface and a diode zone corresponding to a zone occupied by a diode in said first main surface is surrounded by the other of said MOS structure zone and said diode zone.

62. The insulated gate transistor according to claim 50, further comprising:

a third semiconductor layer of said second conductivity type which extends from said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate, is adjacent to said fourth semiconductor layer, and is electrically connected to said second main electrode.

63. An inverter circuit comprising:

the insulated gate transistor according to claim 62 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.

64. The insulated gate transistor according to claim 50, wherein

said fourth semiconductor layer extends from all portions of said second main surface of said semiconductor substrate toward said interior of said semiconductor substrate.

65. An inverter circuit comprising:

the insulated gate transistor according to claim 64 which functions as a switching device with a built-in freewheeling diode of said inverter circuit.