Integrated circuit package having an inductance loop formed from a multi-loop configuration

• US 20050045986A1
• Filed: 08/27/2004
• Published: 03/03/2005
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Lee, Kang Yoon, Lee, Jeong-Woo, Huh, Hyungki, Lee, Kyeongho, Park, Joonbae, Koo, Yido
• Granted Patent: US 7,768,097 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01043 Technetium [Tc]
• CPC Class Codes: H01L 2924/01076 Osmium [Os]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

Claims

1. A semiconductor package, comprising:

an integrated circuit chip; and

an inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor connecting the first input/output pin to the second input/output pin.

2. The semiconductor package of claim 1, wherein the first, second, third, and fourth conductors are bonding wires.

3. The semiconductor package of claim 1, wherein the fifth conductor includes a metallization layer with a substrate of the package.

4. The semiconductor package of claim 3, wherein the metallization layer is on a surface of the substrate.

5. The semiconductor package of claim 3, wherein the metallization layer is included in a sub-surface layer of the substrate.

6. The semiconductor package of claim 1, wherein the fifth conductor includes at least one bonding wire connecting the first input/output pin to the second input/output pin.

7. The semiconductor package of claim 6, wherein the fifth conductor includes at least two bonding wires.

8. The semiconductor package of claim 1, wherein the first input/output pin and the second input/output pin are adjacent pins.

9. The semiconductor package of claim 1, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

10. A semiconductor package, comprising:

an integrated circuit chip; and

an inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and contact one another.

11. The semiconductor package of claim 10, wherein the first, second, third, and fourth conductors are bonding wires.

12. A semiconductor package, comprising:

an integrated circuit chip; and

an inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package; and

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary construction.

13. The semiconductor package of claim 12, wherein the first, second, third, and fourth conductors are bonding wires.

14. A semiconductor package, comprising:

an integrated circuit chip including a phase-locked loop; and

an inductor loop having a length corresponding to an output frequency of the phase-locked loop, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor which connects the first input/output pin to the second input/output pin.

15. The semiconductor package of claim 14, wherein the first, second, third, and fourth conductors are bonding wires.

16. The semiconductor package of claim 14, wherein the fifth conductor includes a metallization layer with a substrate of the package.

17. The semiconductor package of claim 16, wherein the metallization layer is on a surface of the substrate.

18. The semiconductor package of claim 16, wherein the metallization layer is included in a sub-surface layer of the substrate.

19. The semiconductor package of claim 14, wherein the fifth conductor includes at least one bonding wire connecting the first input/output pin to the second input/output pin.

20. The semiconductor package of claim 19, wherein the fifth conductor includes at least two bonding wires.

21. The semiconductor package of claim 14, wherein the first input/output pin and the second input/output pin are adjacent pins.

22. The semiconductor package of claim 14, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

23. A semiconductor package, comprising:

an integrated circuit chip including a phase-locked loop; and

an inductor loop having a length corresponding to an output frequency of the phase-locked loop, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and contact one another.

24. The semiconductor package of claim 23, wherein the first, second, third, and fourth conductors are bonding wires.

25. A semiconductor package, comprising:

an integrated circuit chip including a phase-locked loop; and

an inductor loop having a length corresponding to an output frequency of the phase-locked loop, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package; and

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary construction.

26. The semiconductor package of claim 25, wherein the first, second, third, and fourth conductors are bonding wires.

27. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor connecting the first input/output pin to the second input/output pin.

28. The oscillator circuit of claim 27, wherein the first, second, third, and fourth conductors are bonding wires.

29. The oscillator circuit of claim 27, wherein the fifth conductor includes a metallization layer with a substrate of the package.

30. The oscillator circuit of claim 29, wherein the metallization layer is on a surface of the substrate.

31. The oscillator circuit of claim 29, wherein the metallization layer is included in a sub-surface layer of the substrate.

32. The oscillator circuit of claim 27, wherein the fifth conductor includes at least one bonding wire connecting the first input/output pin to the second input/output pin.

33. The oscillator circuit of claim 32, wherein the fifth conductor includes at least two bonding wires.

34. The oscillator circuit of claim 27, wherein the first input/output pin and the second input/output pin are adjacent pins.

35. The oscillator circuit of claim 27, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

36. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package; and

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and contact one another.

37. The oscillator circuit of claim 36, wherein the first, second, third, and fourth conductors are bonding wires.

38. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package; and

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary construction.

39. The oscillator circuit of claim 38, wherein the first, second, third, and fourth conductors are bonding wires.

40. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package; and

(c) a fifth conductor which connects the first input/output pin to the second input/output pin.

41. The oscillator circuit of claim 40, wherein the first, second, third, and fourth conductors are bonding wires.

42. The oscillator circuit of claim 40, wherein the fifth conductor includes a metallization layer with a substrate of the package.

43. The oscillator circuit of claim 42, wherein the metallization layer is on a surface of the substrate.

44. The oscillator circuit of claim 42, wherein the metallization layer is included in a sub-surface layer of the substrate.

45. The oscillator circuit of claim 40, wherein the fifth conductor includes at least one bonding wire connecting the first input/output pin to the second input/output pin.

46. The oscillator circuit of claim 45, wherein the fifth conductor includes at least two bonding wires.

47. The oscillator circuit of claim 40, wherein the first input/output pin and the second input/output pin are adjacent pins.

48. The oscillator circuit of claim 40, wherein the first input/output pin and the second input/output pin are separated by at least a third input/output pin.

49. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package;

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin are adjacent and contact one another.

50. The oscillator circuit of claim 49, wherein the first, second, third, and fourth conductors are bonding wires.

51. An oscillator circuit, comprising:

an active oscillator having two output nodes;

an inductor loop coupled to the output nodes; and

at least one capacitive circuit coupled to one of the output nodes, said capacitive circuit including a capacitor, a resistor, and a first switch, wherein said resistor provides a bias voltage to the capacitor when the first switch is open and wherein said first switch couples and decouples the capacitor to the output nodes of the active oscillator, and wherein the active oscillator and capacitive circuit are included in a semiconductor package which includes an integrated circuit chip, said inductor loop including;

(a) first and second conductors connecting a first bonding pad on the chip to a first input/output pin of the package; and

(b) at least one of a third conductor and a fourth conductor connecting a second bonding pad on the chip to a second input/output pin of the package, wherein the first input/output pin and the second input/output pin have a unitary construction.

52. The oscillator circuit of claim 51, wherein the first, second, third, and fourth conductors are bonding wires.