Integrated circuit device with embedded passive component by flip-chip connection and method for manufacturing the same

• US 20050046041A1
• Filed: 08/24/2004
• Published: 03/03/2005
• Est. Priority Date: 08/29/2003
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Tsai, Mon-Chin
• Granted Patent: US 7,391,118 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

Claims

1. An integrated circuit device comprising:

a dummy chip having a chip-mounting surface and including at least an embedded component, a plurality of redistribution traces and a plurality of flip-chip pads on the chip-mounting surface, the embedded component being electrically connected to one of the flip-chip pads via one of the redistribution traces;

a flip chip mounted on the chip-mounting surface of the dummy chip, the flip chip having an active surface and a back surface and including a plurality of bonding pads on the active surface; and

a plurality of bumps connecting the bonding pads of the flip chip with the flip-chip pads of the dummy chip.

2. The integrated circuit device in accordance with claim 1, wherein the embedded component is electrically connected to the flip chip.

3. The integrated circuit device in accordance with claim 1, wherein the chip-mounting surface of the dummy chip is larger than the active surface of the flip chip.

4. The integrated circuit device in accordance with claim 3, wherein the dummy chip includes a plurality of ball pads at the peripheral region of the chip-mounting surface, the ball pads are electrically connected to the corresponding flip-chip pads via the redistribution traces.

5. The integrated circuit device in accordance with claim 4, wherein the embedded component is electrically connected to one of the ball pads via one of the redistribution traces.

6. The integrated circuit device in accordance with claim 4, further comprising a plurality of solder balls placed on the ball pads.

7. The integrated circuit device in accordance with claim 6, wherein the solder balls are higher than the back surface of the flip chip.

8. The integrated circuit device in accordance with claim 4, wherein the ball pads are circular in shape and have a diameter larger than that of the flip-chip pads.

9. The integrated circuit device in accordance with claim 1, wherein the dummy chip includes a passivation layer on the chip-mounting surface to cover the redistribution traces and the embedded component.

10. The integrated circuit device in accordance with claim 1, wherein the embedded component is selected from the group consisting of passive component, MEMS component and optical electronic component.

11. The integrated circuit device in accordance with claim 1, wherein the embedded component is selected from the group consisting of capacitor, resistor and inductor.

12. The integrated circuit device in accordance with claim 11, wherein the embedded component is made by a wafer fabrication process.

13. A method for manufacturing an integrated circuit device comprising the steps of:

providing at least a dummy chip having a chip-mounting surface, the dummy chip including at least an embedded component, a plurality of redistribution traces and a plurality of flip-chip pads on the chip-mounting surface, the embedded component being electrically connected to one of the flip-chip pads via one of the redistribution traces;

providing at least a flip chip having an active surface and a back surface, the flip chip including a plurality of bonding pads on the active surface;

mounting the flip chip on the chip-mounting surface of the dummy chip via a plurality of bumps, the bumps connecting the bonding pads of the flip chip with the flip-chip pads of the dummy chip.

14. The method in accordance with claim 13, wherein the dummy chip is formed on a dummy wafer.

15. The method in accordance with claim 13, wherein the dummy chip includes a plurality of ball pads at the peripheral region of the chip-mounting surface, the ball pads are electrically connected to the corresponding flip-chip pads via the redistribution traces.

16. The method in accordance with claim 15, further comprising the step of placing a plurality of solder balls on the ball pads.

17. The method in accordance with claim 16, wherein the solder balls are higher than the back surface of the flip chip.

18. The method in accordance with claim 15, wherein the embedded component is electrically connected to the flip chip.

19. The method in accordance with claim 18, wherein the embedded component is electrically connected to one of the ball pads via one of the redistribution traces.

20. The method in accordance with claim 13, wherein the dummy chip includes a passivation layer on the chip-mounting surface to cover the redistribution traces and the embedded component.

21. The method in accordance with claim 13, wherein the embedded component is selected from the group consisting of passive component, MEMS component and optical electronic component.

22. The method in accordance with claim 13, wherein the embedded component is selected from the group consisting of capacitor, resistor and inductor.