System LSI

• US 20050046434A1
• Filed: 08/26/2003
• Published: 03/03/2005
• Est. Priority Date: 08/26/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Yamasaki, Yoshihiro
• Granted Patent: US 6,993,447 B2
• Time in Patent Office: Days
• US Class Current: 324/762.30
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

A system LSI includes a plurality of circuit blocks; a first power supply terminal, which is connected to a first circuit block; and a second power supply terminal, which is connected to a second circuit block. A first level of test voltage is applied from the first power supply terminal to the first circuit block for a predetermined period of time whereby the first circuit block is tested in operation. A second level of test voltage is applied from the second power supply terminal to the second circuit block for a predetermined period of time whereby the second circuit block is tested in operation independently from the first circuit block.

Claims

1. A system LSI, comprising:

a plurality of circuit blocks;

a first power supply terminal, which is connected to a first circuit block; and

a second power supply terminal, which is connected to a second circuit block, wherein

a first level of test voltage is applied from the first power supply terminal to the first circuit block for a predetermined period of time whereby the first circuit block is tested in operation;

a second level of test voltage is applied from the second power supply terminal to the second circuit block for a predetermined period of time whereby the second circuit block is tested in operation independently from the first circuit block.

2. A system LSI according to claim 1, wherein

the first and second circuit blocks are tested on a wafer before fabrication of the system LSI is completed.

3. A system LSI according to claim 1, wherein

the circuit block and power supply terminal are connected to each other one-by-one,

the first and second circuit blocks are tested on a wafer before fabrication of the system LSI is completed, and

the first and second supply terminals are connected to a common external terminal after the tests are completed.

4. A system LSI according to claim 3, wherein

the first and second supply terminals are connected to the common external terminal in a wire-bonding process.

5. A system LSI according to claim 1, further comprising:

a third circuit block; and

a switching circuit connected both to the first and second power supply terminals and to the third circuit block, wherein

the switching circuit selectively connects the third circuit block to the first and second power supply terminals whereby the third circuit block is tested efficiently.

6. A system LSI according to claim 5, wherein

the first, second and third circuit blocks are tested on a wafer before fabrication of the system LSI is completed.

7. A system LSI according to claim 5, wherein

the circuit blocks and power supply terminals are connected to each other one-by-one,

the first, second and third circuit blocks are tested on a wafer before fabrication of the system LSI is completed, and

the first, second and third supply terminals are connected to a common external terminal after the tests are completed.

8. A system LSI according to claim 5, wherein

the first, second third supply terminals are connected to the common external terminal in a wire-bonding process.