Protection circuit for semiconductor device and semiconductor device including the same

• US 20050047047A1
• Filed: 08/10/2004
• Published: 03/03/2005
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Matsuno, Noriaki
• Granted Patent: US 7,256,599 B2
• Time in Patent Office: Days
• US Class Current: 361/115
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A protection circuit comprises: at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point; a signal generator for applying a signal to the start point of the shielded line; a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

Claims

1. A protection circuit, comprising:

at least one shielded line arranged to cover an area to be protected over a semiconductor device, the at least one shielded line having only one route from a start point to an end point;

a signal generator for applying a signal to the start point of the shielded line;

a counter which starts measurement of time in response to application of the signal to the start point of the shielded line by the signal generator and which ends measurement of the time in response to arrival of the signal at the end point of the shielded line; and

a comparator for comparing the time measured by the counter with a reference value to output a fraud detection signal according to a result of the comparison.

2. The protection circuit of claim 1, wherein the reference value is the time measured by the counter during a period when the shielded line is in a normal state.

3. The protection circuit of claim 1, wherein the comparator performs the comparison in consideration of a variation in the physical characteristics of the shielded line within a guaranteed operating environment of the semiconductor device.

4. The protection circuit of claim 1, wherein the counter performs the measurement of the time by counting a basic clock pulse of the semiconductor device.

5. The protection circuit of claim 1, wherein the counter performs the measurement of the time by counting a clock pulse output from an oscillator provided in the area to be protected over the semiconductor device.

6. The protection circuit of claim 1, wherein;

the protection circuit includes a plurality of said shielded lines;

the signal generator applies a signal to a start point of one of the plurality of shielded lines; and

the protection circuit further includes a switching circuit for notifying the counter about arrival of the signal at the end point of the shielded line to which the signal has been applied.

7. The protection circuit of claim 1, further comprising a signal line in the area to be protected over the semiconductor device, wherein;

the signal generator applies a signal to the start point of the shielded line and an end of the signal line; and

the protection circuit further includes a determination circuit for comparing the signal arriving at the end point of the shielded line and the signal arriving at the other end of the signal line to output a fraud detection signal according to a result of the comparison.

8. The protection circuit of claim 7, wherein the signal generator includes a random number generator.

9. The protection circuit of claim 1, further comprising a failure diagnosis section for applying to the comparator a test signal in substitution for the time measured by the counter and comparing a signal output from the comparator according to the applied test signal with an expected value to output a failure detection signal according to a result of the comparison.

22. A semiconductor device comprising the protection circuit of claim 1.

23. The semiconductor device of claim 22, wherein the semiconductor device shifts in response to the fraud detection signal to a mode in which fraudulent analysis and tampering of information are disabled.

24. The semiconductor device of claim 22, wherein:

the semiconductor device shifts according to the fraud detection circuit to a reset mode or fixed mode which is canceled when the power supply is interrupted; and

if the fraud detection circuit is output a predetermined number of times in series, the semiconductor device shifts to a mode in which fraudulent analysis and tampering of information are disabled.

10. A protection circuit, comprising:

at least one shielded line pair arranged to cover an area to be protected over a semiconductor device, the at least one shielded line pair including two shielded lines which has the same shape and the same length, and each shielded line has only one route from a start point to an end point;

a signal generator for applying a potential to the start points of the shielded lines of the shielded line pair; and

a detector for comparing a potential difference between the end points of the shielded lines of the shielded line pair with a reference value to output a fraud detection signal according to a result of the comparison.

11. The protection circuit of claim 10, wherein:

the protection circuit includes a semiconductor resistor in substitution for one shielded line of the shielded line pair;

the semiconductor resistor is provided in the area to be protected over the semiconductor device and has the same resistive characteristic as that of the one shielded line of the shielded line pair;

the signal generator applies a potential to an end of the semiconductor resistor and a start point of the other shielded line of the shielded line pair; and

the detector compares a potential difference between the other end of the semiconductor resistor and the end point of the other shielded line of the shielded line pair to output a fraud detection signal according to a result of the comparison.

12. The protection circuit of claim 10, wherein;

the protection circuit includes a plurality of said shielded line pairs;

the signal generator applies a potential to start points of shielded lines of one of the plurality of shielded line pairs; and

the protection circuit further includes a switching circuit for transmitting to the detector the potentials at the end points of the shielded line pair to which the potential is applied by the signal generator.

13. The protection circuit of claim 10, further comprising a signal line in the area to be protected over the semiconductor device, wherein

the signal generator applies a signal to the start points of the shielded line pair and an end of the signal line;

and

the protection circuit further includes a determination circuit for comparing signals arriving at the end points of the shielded line pair and a signal arriving at the other end of the signal line to output a fraud detection signal according to a result of the comparison.

14. The protection circuit of claim 13, wherein the signal generator includes a random number generator.

15. The protection circuit of claim 10, further comprising a failure diagnosis section for applying to the detector a test signal in substitution for the potential difference between the end points of the shielded lines of the shielded line pair and comparing a signal output from the detector according to the applied test signal with an expected value to output a failure detection signal according to a result of the comparison.

25. A semiconductor device comprising the protection circuit of claim 10.

26. The semiconductor device of claim 25, wherein the semiconductor device shifts in response to the fraud detection signal to a mode in which fraudulent analysis and tampering of information are disabled.

27. The semiconductor device of claim 25, wherein:

the semiconductor device shifts according to the fraud detection circuit to a reset mode or fixed mode which is canceled when the power supply is interrupted; and

if the fraud detection circuit is output a predetermined number of times in series, the semiconductor device shifts to a mode in which fraudulent analysis and tampering of information are disabled.

16. A protection circuit, comprising:

at least one shielded line pair arranged to cover an area to be protected over a semiconductor device, the at least one shielded line pair including two shielded lines which has the same shape and the same length, and each shielded line has only one route from a start point to an end point;

a signal generator for applying in-phase pulses to the start points of the shielded lines of the shielded line pair; and

a detector for comparing a phase difference between the end points of the shielded lines of the shielded line pair with a reference value to output a fraud detection signal according to a result of the comparison.

17. The protection circuit of claim 16, wherein

the protection circuit includes a plurality of said shielded line pairs;

the signal generator applies the in-phase pulses to start points of shielded lines of one of the plurality of shielded line pairs; and

the protection circuit further includes a switching circuit for transmitting to the detector the potential difference between the end points of the shielded line pair to which the in-phase pulses are applied by the signal generator.

18. The protection circuit of claim 16, wherein

the protection circuit includes a plurality of said shielded line pairs;

the signal generator generates a signal pattern indicating which of the in-phase pulses and pulses having a phase difference are applied to each of the plurality of shielded line pairs and applies the in-phase pulses or the pulses having a phase difference to the start points of each of the plurality of shielded line pairs according to the generated signal pattern; and

the detector compares a phase difference between pulses arriving at the end points of each of the plurality of shielded line pairs with the signal pattern generated by the signal generator to output a fraud detection signal according to a result of the comparison.

19. The protection circuit of claim 18, wherein the signal generator includes a random number generator for generating the signal pattern.

20. The protection circuit of claim 16, further comprising a signal line in the area to be protected over the semiconductor device, wherein

the signal generator applies a signal to the start points of the shielded line pair and an end of the signal line;

and

the protection circuit further includes a determination circuit for comparing signals arriving at the end points of the shielded line pair and a signal arriving at the other end of the signal line to output a fraud detection signal according to a result of the comparison.

21. The protection circuit of claim 16, further comprising a failure diagnosis section for applying to the detector a test signal in substitution for the phase difference between the end points of the shielded lines of the shielded line pair and comparing a signal output from the detector according to the applied test signal with an expected value to output a failure detection signal according to a result of the comparison.

28. A semiconductor device comprising the protection circuit of claim 16.

29. The semiconductor device of claim 28, wherein the semiconductor device shifts in response to the fraud detection signal to a mode in which fraudulent analysis and tampering of information are disabled.

30. The semiconductor device of claim 28, wherein:

the semiconductor device shifts according to the fraud detection circuit to a reset mode or fixed mode which is canceled when the power supply is interrupted; and

if the fraud detection circuit is output a predetermined number of times in series, the semiconductor device shifts to a mode in which fraudulent analysis and tampering of information are disabled.