Semiconductor integrated circuit

• US 20050047265A1
• Filed: 06/15/2004
• Published: 03/03/2005
• Est. Priority Date: 07/30/2003
• Status: Active Grant

• Current Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Renesas Electronics Corporation
• Original Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Saito, Yasuyuki, Yada, Naoki, Koike, Katsunori, Okutsu, Mitsuhiko, Shibatsuka, Yasushi
• Granted Patent: US 7,061,825 B2
• Time in Patent Office: Days
• US Class Current: 365/233.100
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 2005/00143 Avoiding variations of delay due to temperature
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00

Abstract

A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

Claims

1. A semiconductor integrated circuit, comprising:

a memory circuit;

an oscillator circuit which generates an internal clock signal, based on control information stored in the memory circuit; and

a logic circuit which generates control information for causing the frequency of the internal clock signal to coincide with the frequency of an external clock signal generated outside,

wherein the internal clock signal is used for a synchronous operation of an internal circuit.

2. A semiconductor integrated circuit according to claim 1, wherein the logic circuit generates control information in response to instructions for a predetermined operation mode.

3. A semiconductor integrated circuit according to claim 2, wherein the logic circuit performs the operation of generating control information in synchronism with a clock signal generated based on control information initially given to the memory circuit.

4. A semiconductor integrated circuit according to claim 2, wherein the logic circuit performs the operation of generating control information in synchronism with the external clock signal.

5. A semiconductor integrated circuit according to claim 2, wherein the logic circuit performs the operation of generating control information in synchronism with a clock signal generated by another oscillator circuit oscillated in response to instructions for a predetermined operation mode.

6. A semiconductor integrated circuit according to claim 1, further comprising a non-volatile memory device which stores the control information generated by the logic circuit,

wherein the control information stored in the non-volatile memory device is loaded into the memory circuit in response to power-on reset.

7. A semiconductor integrated circuit according to claim 1, further comprising a sampling circuit which samples information that respond to the respective frequencies of the internal clock signal and the external clock signal,

wherein the logic circuit compares the frequencies of the internal clock signal and the external clock signal using the information sampled by the sampling circuit and thereby generates control information which causes an internal clock signal frequency to coincide with an external clock signal frequency.

8. A semiconductor integrated circuit according to claim 1, further comprising a comparator which performs a difference comparison between the frequency of the internal clock signal and the frequency of the external clock signal,

wherein the logic circuit generates control information which allows the internal clock signal frequency to coincide with the external clock signal frequency, using the result of comparison by the comparator.

9. A semiconductor integrated circuit according to claim 7, wherein the logic circuit is a central processing unit and the memory circuit is a register accessible by the central processing unit.

10. A semiconductor integrated circuit according to claim 1,

wherein the memory circuit is a counter, and

wherein the logic circuit performs a difference comparison between the frequency of the internal clock signal and the frequency of the external clock signal and upcounts or downcounts the counter using the result of comparison.

11. A semiconductor integrated circuit according to claim 1, wherein the logic circuit inputs the result of comparison made between the frequency of the internal clock signal and the frequency of the external clock signal from outside and generates control information which causes the internal clock signal frequency to coincide with the external clock signal frequency by reference to the input result of comparison.

12. A semiconductor integrated circuit according to claim 1, further comprising:

a digital/analog converter which analog-converts control data stored in the memory circuit with respect to a conversion reference voltage; and

a bias circuit which forms a bias voltage corresponding to an operating power supply voltage determined based on a voltage outputted from the digital/analog converter,

wherein the oscillator circuit is a voltage-controlled oscillator which uses the voltage determined based on the output voltage of the digital/analog converter as an operating power supply voltage and whose oscillation frequency is controlled by the bias voltage, and

wherein the bias circuit includes a constant current circuit which is provided with MOS transistors each of which meets a gate-to-source voltage condition under which a change in drain-to-source current is small with respect to a change in temperature, and which outputs drain voltages of the MOS transistors as control voltages.

13. A semiconductor integrated circuit according to claim 12,

wherein the constant current circuit includes a p channel type first MOS transistor of which the source receives a power supply voltage and whose gate and drain are short-circuited therebetween, an n channel type second MOS transistor of which the source receives a circuit'"'"'s ground voltage and whose gate and drain are short-circuited therebetween, and a resistive element having one end connected to the drain of the first MOS transistor and the other end connected to the drain of the second MOS transistor, and

wherein the constant current circuit outputs a drain voltage of the first MOS transistor and a drain voltage of the second MOS transistor as control voltages respectively.

14. A semiconductor integrated circuit according to claim 13, wherein the output voltage of the digital/analog converter is supplied as an operating power supply voltage for the voltage-controlled oscillator and the bias circuit via a voltage follower amplifier.

15. A semiconductor integrated circuit according to claim 12, further comprising a reference voltage generator which generates a reference voltage that has compensated for a voltage variation with respect to variations in power supply voltage and temperature,

wherein the digital/analog converter inputs the reference voltage as a conversion reference voltage.

16. A semiconductor integrated circuit according to claim 1, further comprising:

a digital/analog converter which analog-converts control data held in the memory circuit with respect to the conversion reference voltage; and

a bias circuit which forms a bias voltage, based on a voltage outputted from the digital/analog converter,

wherein the oscillator circuit is a voltage-controlled oscillator which includes a CMOS circuit type ring oscillator section and whose oscillation frequency is controlled by the bias voltage for current control with respect to the ring oscillator section, and

wherein the bias circuit applies an operating power supply voltage in the direction to suppress a variation in logical threshold voltage of a CMOS circuit to the oscillator circuit to thereby compensate for variations in the oscillation frequency of the ring oscillator section due to a change in temperature.

17. A semiconductor integrated circuit according to claim 16,

wherein the voltage-controlled oscillator has CMOS inverter delay stages corresponding to odd-numbered stages, which constitute the ring oscillator section, and

wherein the bias circuit has a logical threshold voltage simulation circuit section which simulates a logical threshold voltage of said each CMOS inverter stage, and varies the operating power supply voltage of the oscillator circuit using the output of the logical threshold voltage simulation circuit.

18. A semiconductor integrated circuit according to claim 16, further comprising a reference voltage generator which generates a reference voltage that has compensated for a voltage variation with respect to variations in power supply voltage and temperature,

wherein the digital/analog converter inputs the reference voltage as a conversion reference voltage.

29. A semiconductor integrated circuit according to claim 1, further comprising a variable divider which divides the clock signal outputted from the oscillator circuit.

19. A semiconductor integrated circuit, comprising:

a memory circuit;

an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit; and

a controller which allows the frequency of the internal clock signal to coincide in the outside,

wherein the internal clock signal is used for a synchronous operation of an internal circuit.

20. A semiconductor integrated circuit, comprising:

a memory circuit;

an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit; and

a logic circuit which counts the internal clock signal for each constant interval of a periodically generated pulse and updates the control information in the direction to allow the count value to coincide with an expected value,

wherein the internal clock signal is used for a synchronous operation of an internal circuit.

21. A semiconductor integrated circuit according to claim 20, further comprising an interval generator which periodically generates a constant interval of a pulse,

wherein the interval generator includes a pulse generator, a CR time constant circuit which performs either a charge operation or a discharge operation from a predetermined phase point of a pulse generated from the pulse generator, and a detector which detects that the voltage obtained by the CR time constant circuit reaches a stipulated voltage, and

wherein a time interval from the predetermined phase point to the timing of detection by the detector is defined as the constant interval.

22. A semiconductor integrated circuit according to claim 21, wherein the stipulated voltage is formed based on a reference voltage generated from a reference voltage generator, and the reference voltage is a voltage that has compensated for a voltage variation with respect to variations in power supply voltage and temperature.

23. A semiconductor integrated circuit according to claim 21, wherein the memory circuit is an updown counter.

24. A semiconductor integrated circuit according to claim 23, wherein the updown counter performs upcount or downcount in synchronism with a pulse generated from the pulse generator.

25. A semiconductor integrated circuit according to claim 20, further comprising:

a digital/analog converter which analog-converts control data held in the memory circuit with respect to a conversion reference voltage; and

a bias circuit which forms a bias voltage varied according to a voltage outputted from the digital/analog converter,

wherein the oscillator circuit is a voltage-controlled oscillator whose oscillation frequency is controlled by the bias voltage.

26. A semiconductor integrated circuit according to claim 25, further comprising a reference voltage generator which generates a reference voltage that has compensated for a voltage variation with respect to variations in power supply voltage and temperature,

wherein the digital/analog converter inputs the reference voltage as a conversion reference voltage.

27. A semiconductor integrated circuit according to claim 20, further including a non-volatile memory device,

wherein the non-volatile memory device holds control information initially loaded into the memory circuit in response to power-on reset and the expected value loaded into the logic circuit.

28. A semiconductor integrated circuit according to claim 27, wherein the non-volatile memory device is capable of electrically reprogramming memory information.