Floating gate memory cell, floating gate memory arrangement circuit arrangement and method for fabricating a floating gate memory cell
First Claim
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1. A floating gate memory cell, comprising:
- a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and
a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.
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Abstract
Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.
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Citations
29 Claims
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1. A floating gate memory cell, comprising:
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a first layer having a first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and
a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A floating gate memory cell, comprising:
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a substrate;
a layer sequence formed on the substrate and having a first source/drain region, a channel region arranged on the first source/drain region, and a second source/drain region arranged on the channel region, wherein the first and second source/drain regions are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material;
a first dielectric layer arranged on the surface and side wall regions of the layer sequence and on a portion of the substrate surface that is devoid of the layer sequence;
a floating gate layer arranged on side wall regions of the first dielectric layer, wherein the floating gate layer is formed of a metallically conductive material;
a second dielectric layer arranged on uncovered surfaces of the first dielectric layer and on the floating gate layer; and
a control gate electrode layer arranged on the second dielectric layer, wherein lateral edge sections of the first and second dielectric layers are arranged on the surface of the substrate. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of fabricating a floating gate memory cell, comprising the steps of:
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forming a first layer having first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions; and
forming a floating gate layer on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material. - View Dependent Claims (28)
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29. A method of fabricating a floating gate memory cell, comprising the steps of:
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providing a substrate;
forming a layer sequence on the substrate, the layer sequence having first source/drain layer, a channel layer arranged on the first source/drain layer, and a second source/drain layer arranged on the channel layer, wherein the first and second source/drain layers are formed of a metallically conductive material, and the channel layer is formed of an electrically insulating material;
patterning the layer sequence laterally using a lithography process and an etching process so that a first source/drain region is formed from the first source/drain layer, a channel region is formed from the channel layer, and a second source/drain region is formed from the second source/drain layer;
forming a first dielectric layer on the surface and side wall regions of the layer sequence and on a portion of the substrate surface that is devoid of the layer sequence;
forming a floating gate layer at least partially on side wall regions of the first dielectric layer, wherein the floating gate layer is formed of a metallically conductive material;
forming a second dielectric layer on at least a partial region of on an uncovered surface of the first dielectric layer and on the floating gate layer; and
forming a control gate electrode layer (241) on the second dielectric layer, wherein lateral edge sections of the first and second dielectric layers are formed on the surface of the substrate.
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Specification