Processing device and method for an automatic perception system

• US 20050049828A1
• Filed: 08/09/2002
• Published: 03/03/2005
• Est. Priority Date: 08/10/2001
• Status: Active Grant

• Current Assignee: Image Processing Technologies, LLC (General Patent Corporation), William J. Brown
• Original Assignee: Bevsa
• Inventors: Pirim, Patrick
• Granted Patent: US 7,313,551 B2
• Time in Patent Office: Days
• US Class Current: 702/180
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 5/40 using histogram techniques

Abstract

The invention relates to a processing device for an automatic perception system that involves the use of STN calculation units (1) which receive data from a data bus (7) and which are interconnected by a backannotation bus (6). According to the invention, the units are grouped together in hierarchical sets, in which the set of the order of 0 is formed by a single unit, the set of the order of 1 is formed by the combination of several order 0 set, the sets of the order of P greater than 1 are formed by a combination of lower P−1 order sets, the hierarchised sets of a given order P sharing a backannotation bus. The backannotation buses between a lower order P and a greater order P+1 are interconnected by means of a connection unit. The invention also relates to the method of using the device.

Claims

1. A processing device for an automatic perception system utilizing STN calculation modules (1) receiving data from a data bus (7) and interconnected by a backannotation bus (6), characterized in that the modules are grouped into hierarchized sets comprising the order 0 set formed by one single module, the order 1 set formed by the combining of a plurality of order 0 sets, the order P sets greater than 1, formed by the combination of the lower order P−

1 sets, the hierarchized sets of a given order P sharing a backannotation bus and in that the interconnection of the backannotation bus between a lower order P and a greater order P+1 is done by means of an interconnection module according to an interconnection configuration, a function of selection parameters.

2. The device according to claim 1, wherein the interconnection module comprises:

a first compound term generator (30) receiving on input at least one lower order bus backannotation signal and producing on output a decision-making signal (31) as a function of selection parameters;

at least one second compound term generator (32) receiving on input the greater order backannotation bus (36) and producing on output a signal (33) sent via the lower order backannotation bus as a function of selection parameters;

a third compound term generator (34) receiving on input, on the one hand, the greater order backannotation bus (36) and, on the other hand, the decision-making signal (31) and producing on output a backannotation signal (37) sent via the greater order backannotation bus as a function of selection parameters;

3. The device according to claim 2, wherein in the case of a lower order backannotation bus of dimension I, the first compound term generator (30) receives on input I−

1 backannotation signals, the backannotation signal produced by the second compound term generator (32) being excluded.

4. The device according to claim 2 or 3, wherein in the case of a greater order backannotation bus of dimension S, the second compound term generator (32) receives on input S backannotation signals and the third compound term generator (34) receives on input S−

1 backannotation signals, the backannotation signal produced by the third compound term generator (34) being excluded.

5. The device according to any one of claims 2 to 4, wherein in the case of an interconnection module, whose lower order is 0;

that is, interconnecting a STN calculating module (1) to an order 1 backannotation bus, the STN calculating module (1) comprises an histogram calculating unit (2) performing a calculation as a factor of a parameter selected in a data selection unit (5) arranged between a data bus and the calculating unit (2), said parameter being further taken into account by a classification unit (3) intended to produce a decision-making signal (9), the calculation of the calculating unit (2) is validated by the signal (8) coming from the second compound term generator (32) and wherein the first compound term generator (30) is virtual and produces an output signal equal to the input signal, the decision-making signal being sent directly over the third compound term generator.

6. The device according to any one of claims 2 to 5, wherein the compound term generator comprises:

parameterizable inversion means of input signals E₀, E₁, . . . E_n and producing signals E′

₀, E′

₁, . . . E′

_n;

and AND combination means (101) making it possible to produce on output an out_and signal as a function of the parameters;

out_and=({overscore (Re g₀)}+E′

₀).({overscore (Re g₁)}+E′

₁) . . . ({overscore (Re g_n)}+E′

_n)(Re g₀+Re g₁+ . . . Re g_n)

 

Reg₀, Reg₁, . . . , Reg_n corresponding to the parameters.

7. The device according to claim 6, wherein for the AND combination, the parameters are stored in two groups of n+1 registers, a first register group controlling a first input of a series of n+1 OR EXCLUSIVE gates, whose second input receives the corresponding input signal, a second register group controlling, after inversion (11), a first input of a series of n+1 OR gates, whose second input receives the output signal of the corresponding OR EXCLUSIVE gates, the outputs of the OR gates being combined in an AND gates at n+2 inputs, the AND NOT combination of the inverted outputs of the second group of registers being likewise sent via the AND element, to produces an output signal.

8. The device according to any one of claims 2 to 5, wherein the compound term generator comprises:

parameterizable inversion means of input signals E₀, E₁, . . . E_n and producing signals E′

₀, E′

₁, . . . E′

_n;

OR combination means (102) making it possible to produce on output an out_OR signal as a function of parameters;

out_OR=(Re g₀·

E′

₀)+(Re g₁·

E′

₁)+ . . . (Re g_n·

E′

_n)

 

Reg₀, Reg₁, . . . , Reg_n corresponding to the parameters.

9. The device according to claim 8, wherein for the OR combination, the parameters are stored in two groups of n+1 registers, a first register group controlling a first input of a series of n+1 OR EXCLUSIVE gates, whose second input receives the corresponding input signal, a second register group controlling a first input of a series of n+1 AND gates whose second input receives the output signal from the corresponding OR EXCLUSIVE gates, the outputs of the AND gates being combined in an OR gates having n+1 inputs for producing an output signal.

10. The device according to any one of claims 2 to 5, wherein the compound term generator comprises parameterizable inversion means of input signals E₀, E₁, . . . E_n and producing signals E′

₀, E′

₁, . . . E′

_n, and means making it possible to produce as a function of parameters an output signal out resulting either from an AND combination with;

out=({overscore (Re g₀)}+E′

₀).({overscore (Re g₁)}+E′

₁) . . . ({overscore (Re g_n)}+E′

_n)(Re g₀+Re g₁+ . . . Re g_n)

or an OR combination with;

out=(Re g₀·

E′

₀)+(Re g₁·

E′

₁)+ . . . +(Re g_nE′

)

Reg₀, Reg₁, . . . , Reg_n corresponding to the respective parameters of the combination under consideration.

11. The device according to claim 10, wherein for the AND combination, the parameters are stored in two groups of n+1 registers, a first register group controlling a first input of a series of n+1 OR EXCLUSIVE gates, whose second input receives the corresponding input signal, a second register group controlling, after inversion, a first input of a series of n+1 OR gates, whose second input receives the output signal of the corresponding OR EXCLUSIVE gates, the outputs of the OR gates being combined in an AND gate having n+2 inputs, the AND NOT combination of the inverted outputs of the second group of registers being likewise sent via the AND gate, to produces a first signal and, wherein for the OR combination, the parameters are stored in two groups of n+1 registers, a third register group controlling a first input and a second series of n+1 OR EXCLUSIVE gates, whose second input receives the corresponding input signal, a fourth register group controlling a first input of a series of n+1 AND gates, whose second input receives the output signal from the corresponding OR EXCLUSIVE gates, the outputs of the AND gates being combined in one OR gate having n+1 inputs for producing a second signal, the first signal and the second signal being selected by a multiplexer in order to produce the output signal.

12. The device according to claim 11, wherein the first and third registers as well as the first and second series of OR EXCLUSIVE gates are grouped, respectively, in one single register and one single series of gates, the outputs of the OR EXCLUSIVE gates being sent, on the one hand, via the inputs of the OR gates for the AND combination and, on the other hand, via the inputs of the AND gate for the combination OR.

13. The device according to any one of the above claims, wherein an hierarchized set of modules forms an hierarchized memory of an element of a perception environment and which is defined by the configuration of the selection parameters of the interconnection modules of the set.

14. A processing method for an automatic perception system utilizing STN calculation modules (1) receiving data from a data bus (7) and interconnected by a backannotation bus (6),

characterized in that using a device according to any one of the above claims, the modules are grouped into hierarchized sets comprising the entirety of order 0 formed by a single module, the set of order 1 formed by the combination of a plurality of order 0 sets, the order P sets greater than 1 formed by the combination of lower order P−

1 sets, the hierarchized sets of a given order P sharing a backannotation bus and, wherein the backannotation buses are interconnected between a lower order P and a greater order P+1 by means of an interconnection module according to an interconnection configuration, a function of selection parameters.