Systems and methods for performing circuit analysis on a circuit design

• US 20050050492A1
• Filed: 08/25/2003
• Published: 03/03/2005
• Est. Priority Date: 08/25/2003
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Rogers, Gregory Dennis, Robbert, George Harold, Keller, S. Brandon
• Application Number:
  US10/647,605
• Publication Number:
  US 20050050492A1
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Methods, systems, software products perform circuit analysis on a circuit design. Instantiation paths for one or more design blocks of the circuit design are determined. Select information is recursively accumulated for each of the design blocks. Instantiation characteristics are applied to the accumulated information for each instance of the design blocks based upon instantiation hierarchy of the instance within the circuit design.

Claims

1. A method for performing circuit analysis on a circuit design, comprising:

determining instantiation paths for one or more design blocks of the circuit design;

recursively accumulating select information for each of the design blocks; and

applying instantiation characteristics to the accumulated information for each instance of the design blocks based upon instantiation hierarchy of the instance within the circuit design.

2. The method of claim 1, the select information comprising one or more of FET capacitance, FET width and wire capacitance.

3. The method of claim 1, the instantiation characteristics comprising one or more of switching frequencies and scaling factors.

4. The method of claim 1, the step of recursively accumulating comprising recursively accumulating selected information for one or more HLSN signal nets within the design blocks.

5. The method of claim 4, further comprising selecting the one or more HLSNs through a user interface.

6. The method of claim 1, further comprising selecting the one or more blocks through a user interface.

7. The method of claim 1, further comprising reading instantiation hierarchy from the circuit design to determine the instantiation paths.

8. The method of claim 1, further comprising reading instantiation characteristics from the circuit design.

9. The method of claim 1, further comprising generating results based upon applied instantiation characteristics.

10. A system for performing circuit analysis on a circuit design, comprising:

a user interface for selecting one or more design blocks of the circuit design;

an analysis tool operable to determine instantiation paths for the design blocks, accumulate select information for each instance of each of the design blocks, and apply instantiation characteristics of each instance to the accumulated information; and

memory for storing the instantiation paths, the accumulated information, and results based upon the applied characteristics.

11. The system of claim 10, the select information comprising one or more of FET capacitance, FET width and wire capacitance.

12. The system of claim 10, the instantiation characteristics comprising one or more of switching frequencies and scaling factors.

13. The system of claim 10, the analysis tool operable to recursively accumulate the select information for one or more HLSN signal nets within the design blocks.

14. The system of claim 10, wherein the analysis tool is operable to read an instantiation hierarchy of the circuit design to determine the instantiation paths

15. The system of claim 14, wherein the analysis tool is operable to read the instantiation characteristics from the circuit design.

16. A system for performing circuit analysis on a circuit design, comprising:

means for determining instantiation paths for one or more design blocks of the circuit design;

means for recursively accumulating select information for each of the design blocks; and

means for applying instantiation characteristics to the accumulated information for each instance of the design blocks based upon instantiation hierarchy of the instance within the circuit design.

17. The system of claim 16, the select information comprising one or more of FET capacitance, FET width and wire capacitance.

18. The system of claim 16, the instantiation characteristics comprising one or more of switching frequencies and scaling factors.

19. The system of claim 16, the means for recursively accumulating comprising means for recursively accumulating select information of one or more HLSN signal nets of the design blocks.

20. The system of claim 16, further comprising means for reading instantiation hierarchy from the circuit design to determine the instantiation paths.

21. The system of claim 16, further comprising means for reading instantiation characteristics from the circuit design.

22. The system of claim 16, further comprising means for generating results based upon applied instantiation characteristics.

23. A software product comprising instructions, stored on computer-readable media, wherein the instructions, when executed by a computer, perform steps for performing circuit analysis on a circuit design, comprising:

instructions for determining instantiation paths for one or more design blocks of the circuit design;

instructions for recursively accumulating select information for each of the design blocks; and

instructions for applying instantiation characteristics to the accumulated information for each instance of the design blocks based upon instantiation hierarchy of the instance within the circuit design.

24. The software product of claim 23, the select information comprising one or more of FET capacitance, FET width and wire capacitance.

25. The software product of claim 23, the instantiation characteristics comprising one or more of switching frequencies and scaling factors.

26. The software product of claim 23, wherein the instructions for recursively accumulating comprise instructions for recursively accumulating the select information for one or more HLSN signal nets within the design blocks.

27. The software product of claim 23, further comprising instructions for reading instantiation hierarchy from the circuit design to determine the instantiation paths.

28. The software product of claim 23, further comprising instructions for reading instantiation characteristics from the circuit design.

29. The software product of claim 23, further comprising instructions for generating results based upon applied instantiation characteristics.