System and method for determining unmatched design elements in a computer-automated design
First Claim
1. A method for determining unmatched design elements in a circuit comprising the steps of:
- determining instances of a first type and a second type of the design elements that are connected to a specific node in the circuit;
storing a gate signal name for each determined said instance of the first type of design element in a first list;
storing the gate signal name for each determined said instance of the second type of design element in a second list;
storing a cumulative value of a design element characteristic for each determined said instance of the first and the second types of the design elements;
performing a set difference operation on the first list and the second list to determine orphan gate signal names that appear in either one of the lists but not in both; and
determining a cumulative value for said design element characteristic, by summing the design element characteristic value corresponding to each said first type of design element gate signal name that matches one of said orphan gate signal names, to produce a total design element characteristic value.
2 Assignments
0 Petitions
Accused Products
Abstract
A system and method for determining unmatched design elements in a circuit. The system determines instances of a first type and a second type of the design elements that are connected to a specific node in the circuit, and stores the gate signal name for each determined said occurrence of the first type of design element in a first list. The gate signal name for each determined said occurrence of the second type of design element is than stored in a second list. A value of a design element characteristic and indicia thereof for each determined said occurrence of the first and the second types of the design elements is than stored. A set difference operation is preformed on the first list and the second list to determine orphan gate signal names that appear in only one said list; and a cumulative value is determined for each said design element characteristic, by adding the design element characteristic value corresponding to each stored said orphan gate signal name, to produce a total design element characteristic value.
42 Citations
15 Claims
-
1. A method for determining unmatched design elements in a circuit comprising the steps of:
-
determining instances of a first type and a second type of the design elements that are connected to a specific node in the circuit;
storing a gate signal name for each determined said instance of the first type of design element in a first list;
storing the gate signal name for each determined said instance of the second type of design element in a second list;
storing a cumulative value of a design element characteristic for each determined said instance of the first and the second types of the design elements;
performing a set difference operation on the first list and the second list to determine orphan gate signal names that appear in either one of the lists but not in both; and
determining a cumulative value for said design element characteristic, by summing the design element characteristic value corresponding to each said first type of design element gate signal name that matches one of said orphan gate signal names, to produce a total design element characteristic value. - View Dependent Claims (2, 3)
-
-
4. A method for determining unmatched P-FETs and N-FETs in a circuit comprising the steps of:
-
determining instances of said P-FETs and said N-FETs that are connected to a specific node in the circuit;
storing a gate signal name for each determined said instance of one of said P-FETs in a first list;
storing the gate signal name for each determined said instance of one of said N-FETs in a second list;
storing a cumulative value representing a source current for each determined said instance of said P-FETs and said N-FETs;
performing a set difference operation on the first list and the second list to determine orphan gate signal names that appear in either one of the lists but not in both; and
determining a cumulative value for said source current, by summing the source current value corresponding to each said P-FET gate signal name that matches one of said orphan gate signal names, to produce a total source current value. - View Dependent Claims (5, 6, 7, 8)
-
-
9. A system for determining unmatched design elements in a circuit, comprising:
-
means for determining instances of said P-FETs and said N-FETs that are connected to a specific node in the circuit;
means for storing a gate signal name for each determined said instance of one of said P-FETs in a first list;
means for storing the gate signal name for each determined said instance of one of said N-FETs in a second list;
means for storing a cumulative value representing a source current for each determined said instance of said P-FETs and said N-FETs;
means for performing a set difference operation on the first list and the second list to determine orphan gate signal names that appear in either one of the lists but not in both; and
means for determining a cumulative value for said source current, by summing the source current value corresponding to each said P-FET gate signal name that matches one of said orphan gate signal names, to produce a total source current value.
-
-
10. A system for determining unmatched design elements in a circuit design, comprising:
-
a processor for determining instances of P-FETs and N-FETs that are connected to a specific node in the circuit design;
a first list, located in memory coupled to said processor, for storing a gate signal name for each determined said instance of one of said P-FETs;
a second list, located in said memory coupled to said processor, for storing the gate signal name for each determined said instance of one of said N-FETs in a second list;
a storage mechanism for storing a cumulative value representing a source current for each determined said instance of said P-FETs and said N-FETs;
wherein said processor performs a set difference operation on the first list and the second list to determine orphan gate signal names that appear in either one of the lists but not in both; and
wherein said processor determines a cumulative value for said source current, by summing the source current value corresponding to each said P-FET gate signal name that matches one of said orphan gate signal names, to produce a total source current value. - View Dependent Claims (11, 12, 13, 14)
-
-
15. A software product comprising instructions, stored on computer-readable media, wherein the instructions, when executed by a computer, perform steps for determining unmatched P-FETs and N-FETs in a circuit comprising:
-
determining instances of said P-FETs and said N-FETs that are connected to a specific node in the circuit;
storing a gate signal name for each determined said instance of one of said P-FETs in a first list;
storing the gate signal name for each determined said instance of one of said N-FETs in a second list;
storing a cumulative value representing a source current for each determined said instance of said P-FETs and said N-FETs;
performing a set difference operation on the first list and the second list to determine orphan gate signal names that appear in either one of the lists but not in both; and
determining a cumulative value for said source current, by summing the source current value corresponding to each said P-FET gate signal name that matches one of said orphan gate signal names, to produce a total source current value.
-
Specification