Semiconductor pixel arrays with reduced sensitivity to defects

• US 20050051775A1
• Filed: 09/04/2003
• Published: 03/10/2005
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation Belgium BVBA (Infineon Technologies AG)
• Inventors: Meynants, Guy
• Granted Patent: US 7,408,195 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/68 applied to defects
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organised in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Claims

1. An array of pixel structures which are logically organised in rows and columns, wherein each pixel structure comprises at least two row selection switches or column selection switches coupled in series.

2. An array according to claim 1, wherein the pixel structures are active pixels.

3. An array according to claim 1, wherein at least one of the at least two selection switches is a selection transistor.

4. An array according to claim 3, wherein the selection transistor is a MOSFET.

5. An array according to claim 1, wherein the pixel structures are passive pixels.

6. An array according to claim 1, wherein two selection switches of a pixel structure are each coupled to a separate select line.

7. An array according to claim 1, wherein one row or column of pixel structures shares a plurality of select lines, each nth selection switch of the pixel structures on one row or column being connected to an nth select line.

8. An array according to claim 7, wherein select lines associated with one row or column of pixel structures extend in parallel.

9. An array according to claim 6, furthermore provided with means for driving the select lines.

10. An array according to claim 9, wherein the means for driving the select lines is adapted to apply a same select signal to a plurality of select lines associated with one row or column.

11. An array according to claim 9, wherein the means for driving the select lines is adapted to apply a different select signal to a plurality of select lines associated with one row or column.

12. An array according to claim 6, wherein one of the select lines associated with a row or column of pixel structures is a control line of another row or column of pixel structures.

13. An array according to claim 12, wherein the control line is a reset line.

14. A method for selecting a row or column of pixel structures, respectively, in an array of pixel structures logically organised in rows and columns, the method comprising

selecting the row or column of pixel structures, respectively, by applying a first signal to a first select line associated with the row or column of pixel structures, respectively and, at the same time,

selecting the row or column of pixel structures, respectively, by applying a second signal to a second select line associated with the row or column of pixel structures, respectively.

15. A method according to claim 14, wherein the first and the second signal are the same signals.

16. A method according to claim 14, wherein the first and the second signal are different signals.