STRESS-CONTROLLED DIELECTRIC INTEGRATED CIRCUIT

• US 20050051841A1
• Filed: 06/11/2003
• Published: 03/10/2005
• Est. Priority Date: 04/08/1992
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Leedy, Glenn Joseph
• Granted Patent: US 7,820,469 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1-155. -155. (Canceled).

156. An integrated circuit comprising:

a substrate;

a device layer on said substrate, said device layer having formed therein a plurality of active devices; and

a stress-controlled dielectric layer overlying the device layer;

wherein the integrated circuit is able to have a substantial portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.

157. The apparatus of claim 156, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

158. The apparatus of claim 156, wherein the stress of the stress-controlled dielectric layer is 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

159. The apparatus of claim 158, wherein the stress is tensile.

160. The apparatus of claim 156, wherein the plurality of active devices are semiconductor devices.

161. The apparatus of claim 156, further comprising at least one level of interconnect conductors formed within the stress-controlled dielectric layer.

162. The apparatus of claim 156, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

163. The apparatus of claim 156, wherein a substantial portion of the substrate is removed.

164. The apparatus of claim 156, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

165. The apparatus of claim 156, wherein the integrated circuit has a thickness of about 50 microns or less.

186. The apparatus of claim 156, further comprising:

a second integrated circuit overlying the integrated circuit; and

interconnect connecting portions of the circuitry of the second integrated circuit and the integrated circuit.

187. The apparatus of claim 156, further comprising:

a plurality of integrated circuits overlying the integrated circuit; and

interconnect connecting portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.

191. The apparatus of claim 156, further comprising a dielectric barrier layer in the substrate, wherein the dielectric barrier layer underlies the active devices.

192. The apparatus of claim 156, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit.

193. The apparatus of claim 156, further comprising at least one flexible integrated circuit overlying the integrated circuit.

194. The apparatus of claim 156, wherein the integrated circuit is at least one of elastic and substantially flexible.

195. The apparatus of claim 156, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.

196. The apparatus of claim 156, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

197. The apparatus of claim 156, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

198. The apparatus of claim 156, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

199. The apparatus of claim 198, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

200. The apparatus of claim 156, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

201. The apparatus of claim 156, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

202. The apparatus of claim 156, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

166. An integrated circuit wafer comprising:

a plurality of integrated circuits, each integrated circuit comprising;

a substrate;

a device layer on said substrate, said device layer having formed therein a plurality of active devices; and

a stress-controlled dielectric layer overlying the device layer;

wherein the integrated circuit wafer is able to have a substantial portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.

167. The apparatus of claim 166, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

168. The apparatus of claim 166, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

169. The apparatus of claim 168, wherein the stress is tensile.

170. The apparatus of claim 166, wherein the plurality of active devices are semiconductor devices.

171. The apparatus of claim 166, further comprising at least one level of interconnect conductors formed within the stress-controlled dielectric layer.

172. The apparatus of claim 166, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

173. The apparatus of claim 166, wherein a substantial portion of the substrate is removed.

174. The apparatus of claim 166, wherein the integrated circuit wafer is able to be thinned to about 50 microns or less while retaining its structural integrity.

175. The apparatus of claim 166, wherein the integrated circuit wafer has a thickness of about 50 microns or less.

203. The apparatus of claim 166, further comprising a dielectric barrier layer in the substrate, wherein the dielectric barrier layer underlies the active devices.

204. The apparatus of claim 166, further comprising:

one or more integrated circuits overlying the integrated circuit wafer; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit wafer.

205. The apparatus of claim 166, further comprising at least one flexible integrated circuit overlying the integrated circuit wafer.

206. The apparatus of claim 166, wherein the integrated circuit wafer is at least one of elastic and substantially flexible.

207. The apparatus of claim 166, wherein the integrated circuit wafer is capable of forming at least one of a substantially flexible integrated circuit wafer and an elastic integrated circuit wafer.

208. The apparatus of claim 166, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

209. The apparatus of claim 166, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

210. The apparatus of claim 166, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

211. The apparatus of claim 210, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

212. The apparatus of claim 166, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

213. The apparatus of claim 166, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

214. The apparatus of claim 166, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

176. An integrated circuit comprising:

a substrate having formed thereon circuitry including a plurality of active devices; and

a stress-controlled dielectric layer overlying the active devices;

wherein the integrated circuit is able to have a substantial portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.

177. The apparatus of claim 176, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

178. The apparatus of claim 176, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

179. The apparatus of claim 178, wherein the stress is tensile.

180. The apparatus of claim 176, wherein the plurality of active devices are semiconductor devices.

181. The apparatus of claim 176, further comprising at least one level of interconnect conductors formed within the stress-controlled dielectric layer.

182. The apparatus of claim 176, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

183. The apparatus of claim 176, wherein a substantial portion of the substrate is removed.

184. The apparatus of claim 176, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

185. The apparatus of claim 176, wherein the integrated circuit has a thickness of about 50 microns or less.

188. The apparatus of claim 176, further comprising:

a second integrated circuit overlying the integrated circuit; and

interconnect connecting portions of the circuitry of the second integrated circuit and the integrated circuit.

189. The apparatus of claim 176, further comprising:

a plurality of integrated circuits overlying the integrated circuit; and

interconnect connecting portions of the circuitry of at least one of the plurality of integrated circuits and the integrated circuit.

215. The apparatus of claim 176, further comprising a dielectric barrier layer in the substrate, wherein the dielectric barrier layer underlies the active devices.

216. The apparatus of claim 176, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit.

217. The apparatus of claim 176, further comprising at least one flexible integrated circuit overlying the integrated circuit.

218. The apparatus of claim 176, wherein the integrated circuit is at least one of elastic and substantially flexible.

219. The apparatus of claim 176, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.

220. The apparatus of claim 176, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

221. The apparatus of claim 176, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

222. The apparatus of claim 176, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

223. The apparatus of claim 222, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

224. The apparatus of claim 176, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

225. The apparatus of claim 176, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

226. The apparatus of claim 176, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

190. An integrated circuit comprising:

a substrate having a principal surface;

a device layer formed on the principal surface of the substrate, wherein the device layer has at least one semiconductor device formed in the device layer; and

a stress-controlled dielectric layer overlying the at least one semiconductor device, wherein the integrated circuit is able to have a substantial portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.

227. The apparatus of claim 190, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

228. The apparatus of claim 190, further comprising a dielectric barrier layer in the substrate, wherein the dielectric barrier layer underlies the at least one semiconductor device.

229. The apparatus of claim 190, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

230. The apparatus of claim 229, wherein the stress is tensile.

231. The apparatus of claim 190, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

232. The apparatus of claim 190, wherein a substantial portion of the substrate is removed.

233. The apparatus of claim 190, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the integrated circuit.

234. The apparatus of claim 190, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

235. The apparatus of claim 190, wherein the integrated circuit has a thickness of about 50 microns or less.

236. The apparatus of claim 190, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the at least one semiconductor device of the integrated circuit.

237. The apparatus of claim 190, further comprising at least one flexible integrated circuit overlying the integrated circuit.

238. The apparatus of claim 190, wherein the integrated circuit is at least one of elastic and substantially flexible.

239. The apparatus of claim 190, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.

240. The apparatus of claim 190, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

241. The apparatus of claim 190, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

242. The apparatus of claim 190, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

243. The apparatus of claim 242, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

244. The apparatus of claim 190, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

245. The apparatus of claim 190, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

246. The apparatus of claim 190, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

247. An integrated circuit wafer comprising:

a substrate;

a device layer formed on the substrate, the device layer having formed therein a plurality of active devices; and

a stress-controlled dielectric layer overlying the device layer;

wherein the integrated circuit wafer is able to have a substantial portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.

248. The apparatus of claim 247, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

249. The apparatus of claim 247, further comprising a dielectric barrier layer in the substrate, wherein the dielectric barrier layer underlies the active devices.

250. The apparatus of claim 247, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

251. The apparatus of claim 250, wherein the stress is tensile.

252. The apparatus of claim 247, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

253. The apparatus of claim 247, wherein a substantial portion of the substrate is removed.

254. The apparatus of claim 247, wherein the integrated circuit wafer is able to be thinned to about 50 microns or less while retaining its structural integrity.

255. The apparatus of claim 247, wherein the integrated circuit wafer has a thickness of about 50 microns or less.

256. The apparatus of claim 247, further comprising:

one or more integrated circuits overlying the integrated circuit wafer; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit wafer.

257. The apparatus of claim 247, further comprising at least one flexible integrated circuit overlying the integrated circuit wafer.

258. The apparatus of claim 247, wherein the integrated circuit wafer is at least one of elastic and substantially flexible.

259. The apparatus of claim 247, wherein the integrated circuit wafer is capable of forming at least one of a substantially flexible integrated circuit wafer and an elastic integrated circuit wafer.

260. The apparatus of claim 247, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

261. The apparatus of claim 247, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

262. The apparatus of claim 247, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

263. The apparatus of claim 262, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

264. The apparatus of claim 247, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

265. The apparatus of claim 247, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

266. The apparatus of claim 247, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

267. An integrated circuit comprising:

a substrate;

a device layer formed on the substrate having formed thereon circuitry including a plurality of active devices;

a stress-controlled dielectric layer overlying the plurality of active devices; and

wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit and the integrated circuit is able to have a substantial portion of the substrate removed throughout a full extent thereof while retaining its structural integrity.

268. The apparatus of claim 267, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

269. The apparatus of claim 267, further comprising a dielectric barrier layer in the substrate, the dielectric barrier layer underlying the active devices.

270. The apparatus of claim 267, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

271. The apparatus of claim 270, wherein the stress is tensile.

272. The apparatus of claim 267, wherein the plurality of active devices are semiconductor devices.

273. The apparatus of claim 267, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

274. The apparatus of claim 267, wherein a substantial portion of the substrate is removed.

275. The apparatus of claim 267, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the integrated circuit.

276. The apparatus of claim 267, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

277. The apparatus of claim 267, wherein the integrated circuit has a thickness of about 50 microns or less.

278. The apparatus of claim 267, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit.

279. The apparatus of claim 267, further comprising at least one flexible integrated circuit overlying the integrated circuit.

280. The apparatus of claim 267, wherein the integrated circuit is at least one of elastic and substantially flexible.

281. The apparatus of claim 267, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

282. The apparatus of claim 267, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

283. The apparatus of claim 267, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

284. The apparatus of claim 283, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

285. The apparatus of claim 267, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

286. The apparatus of claim 267, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

287. The apparatus of claim 267, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

288. An integrated circuit comprising:

a device layer having formed thereon circuitry including a plurality of active devices; and

a stress-controlled dielectric layer overlying the plurality of active devices, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

291. The apparatus of claim 288, wherein the plurality of active devices are semiconductor devices.

292. The apparatus of claim 288, further comprising a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

293. The apparatus of claim 288, further comprising a substrate.

294. The apparatus of claim 293, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

295. The apparatus of claim 293, further comprising a dielectric barrier layer in the substrate, the dielectric barrier layer underlying the active devices.

296. The apparatus of claim 293, wherein a substantial portion of the substrate is removed.

297. The apparatus of claim 293, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the integrated circuit.

298. The apparatus of claim 288, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

299. The apparatus of claim 288, wherein the integrated circuit has a thickness of about 50 microns or less.

300. The apparatus of claim 288, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit.

301. The apparatus of claim 288, further comprising at least one flexible integrated circuit overlying the integrated circuit.

302. The apparatus of claim 288, wherein the integrated circuit is at least one of elastic and substantially flexible.

303. The apparatus of claim 288, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.

304. The apparatus of claim 288, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

305. The apparatus of claim 288, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

306. The apparatus of claim 288, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

307. The apparatus of claim 306, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

308. The apparatus of claim 288, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

309. The apparatus of claim 288, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

310. The apparatus of claim 288, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

289. (Cancelled)

290. The apparatus of claim 289, wherein the stress is tensile.

311. An integrated circuit comprising:

a device layer having formed thereon circuitry including a plurality of active devices; and

an elastic dielectric layer overlying the plurality of active devices, wherein the stress of the elastic dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the elastic dielectric layer.

314. The apparatus of claim 311, wherein the plurality of active devices are semiconductor devices.

315. The apparatus of claim 311, further comprising a plurality of interconnect conductors formed within the elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

316. The apparatus of claim 311, further comprising a substrate.

317. The apparatus of claim 316, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

318. The apparatus of claim 316, further comprising a dielectric barrier layer in the substrate, the dielectric barrier layer underlying the active devices.

319. The apparatus of claim 316, wherein a substantial portion of the substrate is removed.

320. The apparatus of claim 316, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the integrated circuit.

321. The apparatus of claim 311, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

322. The apparatus of claim 311, wherein the integrated circuit has a thickness of about 50 microns or less.

323. The apparatus of claim 311, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit.

324. The apparatus of claim 311, further comprising at least one flexible integrated circuit overlying the integrated circuit.

325. The apparatus of claim 311, wherein the integrated circuit is at least one of substantially flexible and elastic.

326. The apparatus of claim 311, wherein the integrated circuit is capable of forming at least one of a substantially flexible integrated circuit and an elastic integrated circuit.

327. The apparatus of claim 311, wherein the elastic dielectric layer is substantially flexible.

328. The apparatus of claim 311, wherein the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

329. The apparatus of claim 311, wherein the elastic dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

330. The apparatus of claim 329, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

331. The apparatus of claim 311, wherein the elastic dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

332. The apparatus of claim 311, wherein the elastic dielectric layer is formed by multiple RF energy sources.

333. The apparatus of claim 311, wherein the elastic dielectric layer is formed at a temperature of about 400°

C.

312. (Cancelled).

313. The apparatus of claim 312, wherein the stress is tensile.

334. A circuit interconnect comprising:

a substrate;

a stress-controlled dielectric layer overlying the substrate; and

a plurality of interconnect conductors formed within the stress-controlled dielectric layer, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the circuit interconnect.

335. The apparatus of claim 334, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

336. The apparatus of claim 334, wherein the stress of the stress-controlled dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the stress-controlled dielectric layer.

337. The apparatus of claim 336, wherein the stress is tensile.

338. The apparatus of claim 334, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors

339. The apparatus of claim 334, wherein the substrate is removed.

340. The apparatus of claim 334, wherein a substantial portion of the substrate is removed.

341. The apparatus of claim 334, further comprising removing the substrate, wherein the remaining circuit interconnect is at least one of a substantially flexible interconnect circuit, an elastic interconnect circuit and a free standing interconnect circuit.

343. The apparatus of claim 334, wherein the circuit interconnect is able to be thinned to about 50 microns or less while retaining its structural integrity.

344. The apparatus of claim 334, wherein the circuit interconnect has a thickness of about 50 microns or less.

345. The apparatus of claim 334, further comprising:

one or more integrated circuits overlying the circuit interconnect; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of interconnect conductors of the circuit interconnect.

346. The apparatus of claim 334, further comprising at least one flexible integrated circuit overlying the circuit interconnect.

347. The apparatus of claim 334, wherein the circuit interconnect is at least one of elastic and substantially flexible.

348. The apparatus of claim 334, wherein the stress-controlled dielectric layer is at least one of elastic and substantially flexible.

349. The apparatus of claim 334, wherein the stress-controlled dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

350. The apparatus of claim 334, wherein the stress-controlled dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

351. The apparatus of claim 350, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

352. The apparatus of claim 334, wherein the stress-controlled dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

353. The apparatus of claim 334, wherein the stress-controlled dielectric layer is formed by multiple RF energy sources.

354. The apparatus of claim 334, wherein the stress-controlled dielectric layer is formed at a temperature of about 400°

C.

342. (Cancelled).

355. An integrated circuit comprising:

a thin substrate; and

circuitry formed on the substrate, wherein the circuitry includes a plurality active devices;

wherein the integrated circuit is at least one of a substantially flexible integrated circuit and an elastic integrated circuit, while retaining its structural integrity.

356. The apparatus of claim 355, wherein said thin substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

357. The apparatus of claim 355, further comprising a dielectric barrier layer in the substrate, the dielectric barrier layer underlying the active devices.

358. The apparatus of claim 355, further comprising at least one elastic dielectric layer overlying said plurality of active devices.

359. The apparatus of claim 358, wherein the stress of the at least one elastic dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer.

360. The apparatus of claim 359, wherein the stress is tensile stress.

361. The apparatus of claim 358, further comprising a plurality of interconnect conductors formed within the at least one elastic dielectric layer, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

362. The apparatus of claim 355, wherein the plurality of active devices are inorganic active devices.

363. The apparatus of claim 355, wherein the integrated circuit has a thickness of about 50 microns or less.

364. The apparatus of claim 355, wherein the integrated circuit is able to be thinned to about 50 microns or less while retaining its structural integrity.

365. The apparatus of claim 355, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the integrated circuit.

366. The apparatus of claim 355, further comprising:

one or more integrated circuits overlying the integrated circuit; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of active devices of the integrated circuit.

367. The apparatus of claim 358, wherein the at least one elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

368. The apparatus of claim 358, wherein the at least one elastic dielectric layer is formed from at least one of an inorganic and an organic dielectric material.

369. The apparatus of claim 368, wherein the inorganic dielectric material is one of silicon dioxide and silicon nitride.

370. The apparatus of claim 358, wherein the at least one elastic dielectric layer is substantially flexible.

371. The apparatus of claim 358, wherein the at least one elastic dielectric layer is formed by multiple RF energy sources.

372. The apparatus of claim 358, wherein the at least one elastic dielectric layer is at least one of an inorganic dielectric material and an organic dielectric material.

373. The apparatus of claim 372, wherein the inorganic dielectric material is at least one of silicon dioxide and silicon nitride.

374. The apparatus of claim 358, wherein the at least one elastic dielectric layer is formed by at least one of Chemical Vapor Deposition and Plasma Enhanced Chemical Vapor Deposition.

375. The apparatus of claim 358, wherein the at least one elastic dielectric layer is formed at a temperature of about 400°

C.