Clock distribution networks and conductive lines in semiconductor integrated circuits
First Claim
1. An apparatus comprising a first semiconductor integrated circuit comprising:
- a first surface and a second surface that are opposite to each other; and
a clock distribution network having an input terminal which is a contact pad at the second surface and having a plurality of output terminals which are contact pads at the first surface.
1 Assignment
0 Petitions
Accused Products
Abstract
A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.
38 Citations
33 Claims
-
1. An apparatus comprising a first semiconductor integrated circuit comprising:
-
a first surface and a second surface that are opposite to each other; and
a clock distribution network having an input terminal which is a contact pad at the second surface and having a plurality of output terminals which are contact pads at the first surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. An integrated circuit comprising:
-
a semiconductor substrate having a trench therein; and
a conductive line formed in the trench and interconnecting two laterally spaced nodes of the integrated circuit. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33-45. -45 (cancelled).
Specification