Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states

• US 20050052915A1
• Filed: 09/29/2004
• Published: 03/10/2005
• Est. Priority Date: 12/19/2002
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Herner, S. Brad, Walker, Andrew J.
• Granted Patent: US 8,637,366 B2
• Time in Patent Office: Days
• US Class Current: 365/202
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Claims

1. A programmable memory cell comprising:

a first conductor extending in a first direction;

a vertical pillar consisting essentially of semiconductor material and conductivity-enhancing dopants and having a top surface and a bottom surface;

a second conductor above the first conductor extending in a second direction different from the first direction,

wherein the vertical pillar is disposed between the first and second conductors and

wherein the top surface and the bottom surface are in electrical contact with the first and second conductors, and

wherein, before programming of the memory cell, an unprogrammed current flows between the conductors when a read voltage is applied and

wherein, after programming of the memory cell, a programmed current flows between the conductors when the same read voltage is applied,

wherein a difference between the unprogrammed and programmed currents is sufficient for an unprogrammed state and an programmed state of the memory cell to be reliably distinguishable.

2. The memory cell of claim 1 wherein the vertical pillar comprises silicon.

3. The memory cell of claim 2 wherein the vertical pillar comprises germanium.

4. The memory cell of claim 1 wherein the vertical pillar comprises germanium.

5. The memory cell of claim 1 wherein, after programming of the memory cell, the vertical pillar functions as a junction diode.

6. The memory cell of claim 5 wherein the vertical pillar comprises a heavily doped p-type region and a heavily doped n-type region.

7. The memory cell of claim 1 wherein the vertical pillar comprises doped regions of one conductivity type only.

8. The memory cell of claim 7 wherein the vertical pillar functions as a resistor.

9. The memory cell of claim 1 wherein the read voltage is between about 0.5 volts and about 4 volts.

10. The memory cell of claim 9 wherein the read voltage is between about 0.8 volts and about 3 volts.

11. The memory cell of claim 1 wherein the read voltage is between about 1 volt and about 2 volts.

12. The memory cell of claim 1 wherein the memory cell is programmed by application of a programming voltage, the programming voltage between about 2 volts and about 18 volts.

13. The memory cell of claim 12 wherein the memory cell is programmed by application of a programming voltage, the programming voltage between about 2.5 volts and about 8 volts.

14. The memory cell of claim 13 wherein the memory cell is programmed by application of a programming voltage, the programming voltage between about 3 volts and about 5 volts.

15. The memory cell of claim 1 wherein the first or the second conductor does not comprise semiconductor material.

16. The memory cell of claim 15 wherein the first or the second conductor comprises a metal.

17. The memory cell of claim 16 wherein the first or the second conductor comprises tungsten.

18. The memory cell of claim 1 wherein the difference between the unprogrammed current and the programmed current is at least two orders of magnitude.

19. The memory cell of claim 18 wherein the difference between the unprogrammed current and the programmed current is at least three orders of magnitude.

20. The memory cell of claim 1 wherein the unprogrammed current is less than or equal to about 3.5×

10<sup>−

8</sup> amps.

21. The memory cell of claim 1 wherein the unprogrammed current density is less than or equal to about 4.4×

10<sup>−

6</sup> amp/micron².

22. The memory cell of claim 1 wherein the programmed current is more than or equal to about 3×

10<sup>−

5</sup> amps.

23. The memory cell of claim 1 wherein the programmed current density is more than or equal to about 3.82×

10<sup>−

3</sup> amp/micron².

24. The memory cell of claim 1 wherein the semiconductor material is not in contact with a silicide.

25. An array of memory cells, the array comprising:

a plurality of substantially parallel, substantially coplanar first conductors extending in a first direction;

a plurality of vertically oriented semiconductor pillars above and in electrical contact with the first conductors, wherein the pillars do not comprise a dielectric layer formed by deposition or a thermal or plasma oxidation or nitridation process exceeding 100 degrees C.; and

a plurality of substantially parallel, substantially coplanar second conductors extending in a second direction different from the first direction, the second conductors above and in electrical contact with the pillars,

wherein the first and second conductors and the pillars form a level of programmable memory cells disposed above a substrate.

26. The array of claim 25 wherein the programmable memory cells are programmed by application of a programming voltage.

27. The array of claim 26 wherein the programming voltage is between about 2 volts and about 18 volts.

28. The array of claim 27 wherein the programming voltage is between about 2.5 volts and about 8 volts.

29. The array of claim 28 wherein the programming voltage is between about 3 volts and about 5 volts.

30. The array of claim 25 wherein the pillars comprise conductivity-enhancing dopants.

31. The array of claim 30 wherein each pillar comprises a p-doped region and an n-doped region.

32. The array of claim 30 wherein each pillar comprises doped regions of only one conductivity type.

33. A monolithic three dimensional memory array, the array comprising:

a) a first memory level, the first memory level comprising;

i) a plurality of substantially parallel first conductors formed above a monocrystalline substrate;

ii) a plurality of first vertical pillars consisting essentially of semiconductor material and conductivity-enhancing dopants, the first pillars above and in electrical contact with the first conductors; and

iii) a plurality of substantially parallel second conductors formed above the first pillars, the first pillars in electrical contact with the second conductors,

wherein the first conductors, first pillars, and second conductors make up a first plurality of unprogrammed memory cells; and

b) a second memory level monolithically formed above the first memory level.

34. The memory array of claim 33 wherein the second memory level comprises the second conductors, and further comprises a plurality of second vertical pillars above and in electrical contact with the second conductors.

35. The memory array of claim 34 wherein the second memory level further comprises a plurality of substantially parallel third conductors above and in electrical contact with the second pillars.

36. The memory array of claim 33 wherein each first pillar is in electrical contact with one first conductor and one second conductor.

37. The memory array of claim 33 wherein each of the first pillars comprises a p-doped region and an n-doped region.

38. The memory array of claim 33 wherein each of the first pillars comprises heavily doped p-type regions but no heavily doped n-type regions.

39. The memory array of claim 33 wherein each of the first pillars comprises heavily doped n-type regions but no heavily doped p-type regions.

40. The memory array of claim 33 wherein the first pillars comprise silicon.

41. The memory array of claim 33 wherein the first pillars comprises germanium.

42. The memory array of claim 33 wherein the first pillars comprise silicon-germanium.

43. A method for forming a memory cell, the method comprising:

forming a first elongate conductor having a top layer;

forming a vertical polycrystalline or amorphous pillar, the pillar consisting essentially of semiconductor material and comprising both an n-doped and a p-doped region, the pillar formed over and in electrical contact with the first conductor; and

forming a second conductor over the pillar, the second conductor having a bottom layer, wherein the pillar is in electrical contact with the second conductor,

wherein the top layer of the first conductor does not comprise semiconductor material and

wherein the bottom layer of the second conductor does not comprise semiconductor material.

44. The method of claim 43 wherein the top layer of the first conductor comprises a metal.

45. The method of claim 43 wherein the top layer of the first conductor comprises a silicide.

46. The method of claim 43 wherein the top layer of the first conductor comprises titanium nitride, tantalum nitride, or tungsten nitride.

47. The method of claim 43 wherein the pillar comprises silicon.

48. The method of claim 43 wherein the pillar comprises germanium.

49. The method of claim 43 wherein the pillar comprises a silicon-germanium alloy.

50. The method of claim 43 wherein the step of forming the pillar comprises:

depositing a layer stack of semiconductor material; and

etching and patterning the layer stack to form the pillar.

51. A method for forming a memory cell, the method comprising:

forming a first conductor having a top layer;

forming a layer stack consisting essentially of doped semiconductor material;

patterning and etching the layer stack to form a semiconductor pillar in electrical contact with the top layer of the first conductor;

forming a second conductor over the pillar, the second conductor having a bottom layer, wherein the pillar is in electrical contact with the second conductor,

wherein the top layer of the first conductor does not comprise semiconductor material and

wherein the bottom layer of the second conductor does not comprise semiconductor material.

52. The method of claim 51 wherein the pillar comprises silicon.

53. The method of claim 51 wherein the pillar comprises germanium.

54. The method of claim 51 wherein the pillar comprises silicon-germanium.

55. The method of claim 51 wherein the pillar comprises conductivity-enhancing dopants.

56. The method of claim 55 wherein the pillar comprises both a p-type region and an n-type region.

57. The method of claim 55 wherein the pillar comprises a p-type region but no n-type region.

58. The method of claim 55 wherein the pillar comprises an n-type region but no p-type region.

59. The method of claim 51 wherein the top layer of the bottom conductor comprises a metal.

60. The method of claim 51 wherein the top layer of the bottom conductor comprises a silicide.

61. A method for forming a memory array, the method comprising:

forming a plurality of substantially parallel first conductors;

depositing a layer stack consisting essentially of semiconductor material and conductivity-enhancing dopants;

patterning and etching the layer stack of semiconductor material to form a plurality of first pillars, each first pillar in electrical contact with a first conductor; and

forming second conductors above the first pillars, each first pillar in electrical contact with a second conductor, wherein

the array so formed comprises programmable memory cells.

62. The method of claim 61 wherein the step of forming the first conductors comprises:

depositing a first conductive material;

patterning and etching the first conductive material into first conductors;

depositing first dielectric fill over and between the first conductors; and

planarizing the first dielectric fill to expose a top surface of the first conductors.

63. The method of claim 62 wherein the step of depositing a layer stack comprises depositing a layer stack on the planarized first dielectric fill and first conductors.

64. The method of claim 63 further comprising, after patterning and etching the layer stack:

depositing second dielectric fill over and between the first pillars;

planarizing the second dielectric fill to expose a top surface of the first pillars.

65. The method of claim 61 wherein each of the pillars comprises a heavily doped n-type region and a heavily doped p-type region.

66. The method of claim 61 wherein each of the pillars comprises a heavily doped n-type region and does not comprise a heavily doped p-type region.

67. The method of claim 61 wherein each of the pillars comprises a heavily doped p-type region and does not comprise a heavily doped n-type region.

68. The method of claim 61 wherein the pillars comprise silicon.

69. The method of claim 61 wherein the pillars comprise germanium.

70. The method of claim 61 wherein the pillars comprise silicon-germanium.

71. The method of claim 61 wherein the programmable memory cells are programmed by applying a programming voltage.

72. The method of claim 71 wherein the programming voltage is between about 2 and about 18 volts.

73. The method of claim 72 wherein the programming voltage is between about 2.5 and about 8 volts.

74. The method of claim 73 wherein the programming voltage is between about 3 and about 5 volts.

82. The method of claim 73 wherein the first pillars comprise silicon.

83. The method of claim 73 wherein the first pillars comprise germanium.

84. The method of claim 73 wherein the first pillars comprise silicon-germanium.

85. The method of claim 73 wherein each of the first pillars comprises a junction diode.

96. The memory cell of claim 85 wherein the read voltage is between about 1 volt and about 2 volts.

97. The memory cell of claim 85 wherein the memory cell is programmed by application of a programming voltage, the programming voltage between about 2 volts and about 18 volts.

98. The memory cell of claim 97 wherein the memory cell is programmed by application of a programming voltage, the programming voltage between about 2.5 volts and about 8 volts.

99. The memory cell of claim 98 wherein the memory cell is programmed by application of a programming voltage, the programming voltage between about 3 volts and about 5 volts.

100. The memory cell of claim 85 wherein the first or the second conductor comprises a metal.

101. The memory cell of claim 100 wherein the first or the second conductor comprises tungsten.

102. The memory cell of claim 85 wherein the difference between the unprogrammed current and the programmed current is at least two orders of magnitude.

103. The memory cell of claim 102 wherein the difference between the unprogrammed current and the programmed current is at least three orders of magnitude.

104. The memory cell of claim 85 wherein the unprogrammed current is less than or equal to about 3.5×

10<sup>−

8</sup> amps.

105. The memory cell of claim 85 wherein the unprogrammed current density is less than or equal to about 4.4×

10<sup>−

6</sup> amp/micron².

106. The memory cell of claim 85 wherein the programmed current is more than or equal to about 3×

10<sup>−

5</sup> amps.

107. The memory cell of claim 85 wherein the programmed current density is more than or equal to about 3.82×

10<sup>−

3</sup> amp/micron².

108. The memory cell of claim 85 wherein the semiconductor material is not in contact with a silicide.

75. A method for forming a monolithic three dimensional memory array, the method comprising:

forming a plurality of substantially parallel first conductors extending in a first direction;

forming a plurality of first amorphous or polycrystalline semiconductor pillars, wherein the first pillars do not comprise a deposited dielectric layer and wherein the step of forming the first pillars does not comprise a plasma or thermal oxidation or nitridation step performed at temperatures greater than about 100 degrees C., and

 

wherein each first pillar is above and in electrical contact with one of the first conductors;

forming a plurality of substantially parallel second conductors over the first pillars, the second conductors extending in a second direction different from the first direction, each first pillar in electrical contact with at least one second conductor; and

forming a plurality of second semiconductor pillars, each second pillar above and in electrical contact with a second conductor.

76. The method of claim 75 wherein the step of forming first conductors comprises:

depositing a first layer of conductive material;

patterning and etching the first layer of conductive material into the first conductors;

depositing first dielectric fill over and between the first conductors; and

planarizing the first dielectric fill to expose a top surface of the first conductors.

77. The method of claim 76 wherein the step of forming first pillars comprises:

depositing semiconductor material on the planarized first dielectric fill and first conductors;

patterning and etching the semiconductor material to form first pillars;

depositing second dielectric fill over and between the first pillars; and

planarizing the second dielectric fill to expose a top surface of the first pillars.

78. The method of claim 75 further comprising forming a plurality of substantially parallel third conductors over the second pillars, each second pillar in electrical contact with a third conductor.

79. The method of claim 75 wherein the first conductors, first pillars, and second conductors form a first memory level.

80. The method of claim 79 wherein the second conductor, second pillars, and third conductors form a second memory level.

81. The method of claim 78 further comprising forming at least one additional memory level above the first and second memory levels.

86. A programmable memory cell comprising:

a first conductor extending in a first direction;

a vertical pillar consisting essentially of semiconductor material and conductivity-enhancing dopants and having a top surface and a bottom surface;

a second conductor above the first conductor extending in a second direction different from the first direction,

wherein the vertical pillar is disposed between the first and second conductors, and

wherein, before programming of the memory cell, an unprogrammed current flows between the conductors when a read voltage is applied and

wherein, after programming of the memory cell, a programmed current flows between the conductors when the same read voltage is applied,

wherein a difference between the unprogrammed and programmed currents is sufficient for an unprogrammed state and an programmed state of the memory cell to be reliably distinguishable.

87. The memory cell of claim 86 wherein the vertical pillar comprises silicon.

88. The memory cell of claim 87 wherein the vertical pillar comprises germanium.

89. The memory cell of claim 86 wherein the vertical pillar comprises germanium.

90. The memory cell of claim 86 wherein, after programming of the memory cell, the vertical pillar functions as a junction diode.

91. The memory cell of claim 90 wherein the vertical pillar comprises a heavily doped p-type region and a heavily doped n-type region.

92. The memory cell of claim 86 wherein the vertical pillar comprises doped regions of one conductivity type only.

93. The memory cell of claim 92 wherein the vertical pillar functions as a resistor.

94. The memory cell of claim 86 wherein the read voltage is between about 0.5 volts and about 4 volts.

95. The memory cell of claim 94 wherein the read voltage is between about 0.8 volts and about 3 volts.