Event and relationship timepiece

• US 20050052954A1
• Filed: 09/05/2003
• Published: 03/10/2005
• Est. Priority Date: 09/05/2003
• Status: Abandoned Application

• Current Assignee: Martin Riedi
• Original Assignee: Martin Riedi
• Inventors: Valderrama, Christian, Riedi, Martin
• Application Number:
  US10/656,030
• Publication Number:
  US 20050052954A1
• Time in Patent Office: Days
• US Class Current: 368/110
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means

Abstract

A timepiece structured to record and display the elapsed time from at least one specific event to the current time including a processor having a chronographic application structured to record the elapsed time on a continuous basis. The processor also includes a restrictive designation application structured to restrict resetting of the timepiece, or the chronographic application associated therewith, by a user thereof, with a different event. A memory capability is included for storing one or more original input times of associated events, wherein the timepiece and/or the chronographic application can be reset only by entry through a restrictive access to the memory capability, such as may be accomplished by the an authorized processing facility, rather than the user or owner of the timepiece. The elapsed time of a selected specific event is thereby “permanently” and continuously recorded for display by restricting the ability to reset or stop the timepiece.

Claims

1. A timepiece structured to determine the elapsed time from a specific event, said timepiece comprising:

a) a housing including a display assembly structured to display elapsed time,

b) a processor including a chronographic application determinative of the elapsed time,

c) an activation assembly cooperatively structured with said processor to selectively instigate monitoring of the elapsed time from the specific event to the current time, and

d) said processor further comprising a restrictive designation application structured to at least initially limit selection of the specif event to a single occurrence.

2. A timepiece as recited in claim 1 wherein said display assembly is structured to display current elapsed time in at least one time interval.

3. A timepiece as recited in claim 2 wherein said display assembly is structured to display current elapsed time in a plurality of different time intervals.

4. A timepiece as recited in claim 2 wherein said display assembly is structured to display current elapsed time concurrently in a plurality of different time intervals.

5. A timepiece assembly as recited in claim 4 wherein said plurality of time intervals alternatively comprise two different pairs of time intervals.

6. A timepiece as recited in claim 1 wherein said restrictive designation application is structured to restrict resetting of said chronographic application.

7. A timepiece as recited in claim 6 wherein said processor comprises a memory capability structured to store an original input time of the specific event.

8. A timepiece as recited in claim 7 wherein said processor further comprises a limited access application structured to restrict access to said memory capability and any original input time stored therein.

9. A timepiece as recited in claim 8 wherein said memory capability is accessed and said original input time stored therein is accessed by defeat of said limited access application.

10. A timepiece as recited in claim 9 wherein said chronographic application is responsive to said defeat of said limited access application at least to the extent of being reset.

11. A timepiece as recited in claim 10 wherein said chronographic application is operable to determine current elapsed time subsequent to the resetting thereof to a corresponding original input time.

12. A timepiece as recited in claim 1 wherein said processor further comprises a memory capability structured to store an original input time of at least one specific event.

13. A timepiece as recited in claim 12 wherein said memory capability is further structured to store a plurality of original input times, each of said plurality of original input times associated with an occurrence of a different specific event.

14. A timepiece as recited in claim 12 wherein said restrictive designation application is structured to restrict resetting of said chronographic application to said original input time or a new input time subsequent to a predetermined adjustment time period and instigation of time monitoring by said chronographic application.

15. A timepiece as recited in claim 12 wherein said memory capability is operative to automatically restore said original input time to said chronographic application in the event of a power failure.

16. A timepiece structured to determine the elapsed time from at least one specific event, said timepiece comprising:

a) a housing including a display assembly structured to display elapsed time,

b) a processor including a chronographic application determinative of the elapsed time from the specific event to the current time,

c) said processor including a memory capability structured to store at least one original input time of an associated specific event,

d) an activation assembly operative with said chronographic application and structured to instigate continuous monitoring by said chronographic application of elapsed time from the specific event to the current time, and

e) said processor further comprising a restrictive designation application structured to initially limit selection of a predetermined number of specific events being monitored by said chronographic application.

17. A timepiece as recited in claim 16 wherein said restrictive designation application is structured to restrict resetting of said chronographic application.

18. A timepiece as recited in claim 17 wherein said restrictive designation application is structured to restrict resetting of said chronographic application by entry of an original input time for a specific event other than original input times associated with said predetermined numbers specific events.

19. A timepiece as recited in claim 16 wherein said restrictive designation application is structured to restrict entry of original input time for a specific event other than original input times associated with said predetermined number of specific events.

20. A timepiece as recited in claim 16 wherein said processor further comprises a limited access application structured to restrict access to said memory capability and an original input time of an associated specific event stored therein.

21. A timepiece as recited in claim 20 wherein said memory capability is accessed and said original input time is restored to said chronographic application by defeat of said limited access application.

22. A timepiece as recited in claim 16 wherein said display assembly is structured to display current elapsed time concurrently in a plurality of time intervals.

23. A timepiece as recited in claim 16 wherein said memory capability is operative to automatically restore said original input time to said chronographic application in the event of a power failure.

24. A timepiece structured to determine the elapsed time from at least one specific event, said timepiece comprising:

a) a housing including a display assembly structured to display elapsed time,

b) a processor including a chronographic application determinative of the elapsed time,

c) an activation assembly operative with said chronographic application and structured to instigate continuous monitoring by said chronographic application of elapsed time from the specific event to a current time, and

d) said processor further comprising a restrictive designation application structured to restrict resetting of said chronographic application to any original input time subsequent to instigation of elapsed time monitoring by said chronographic application.

25. A timepiece as recited in claim 24 wherein said processor further comprises a memory capability structured to store at least one original input time of an associated specific event.

26. A timepiece as recited in claim 25 wherein said processor further comprises a limited access application structured to restrict access to said memory capability and an original input time of an associated specific event stored therein.

27. A timepiece as recited in claim 26 wherein said memory capability is accessed and said original input time is restored to said chronographic application by defeat of said limited access application.