Method to improve the resolution of time measurements and alignment in packet networks by time modulation

• US 20050053076A1
• Filed: 07/21/2003
• Published: 03/10/2005
• Est. Priority Date: 07/21/2003
• Status: Active Grant

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Inventors: Van Der Valk, Robertus L., Simons, Petrus W., Repko, Willem L., Roos, Steven
• Granted Patent: US 7,385,990 B2
• Time in Patent Office: Days
• US Class Current: 370/395.620
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/12 Arrangements providing for calling or supervisory signals
• CPC Class Codes: H04J 9/00 Multiplex systems in which each channel is represented by a different type of modulation of the carrier

Abstract

A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network.

Claims

1. In a method of recovering timing information in a packet network, the improvement wherein a modulated signal is used to transport additional information required for clock recovery between the sender and receiver across the network.

2. The method of claim 1, wherein said modulated signal is frequency or phase modulated.

3. The method of claim 2, wherein said modulated signal is manifested as an offset in the rate of transmission of packets from the sender.

4. The method of claim 3, wherein offset is an odd fraction f of a cycle of a clock signal wherein the timing error at the receiver contains only high frequency components.

5. The method of claim 4, wherein f is {fraction (5/32)}.

6. The method of claim 5, wherein f is {fraction (27/32)}.

7. The method of claim 4, wherein the packet rate is offset by an amount equal to the ratio of the packet cycle and clock cycle multiplied by f.

8. The method of claim 4, wherein said high frequency components are filtered out at the receiver.

9. The method of claim 1, wherein a phase locked loop is provided at the receiver to remove timing errors arising between the last node in the path of a packet across the network and the receiver.

10. The method of claim 1, wherein said modulated signal uses sinusoidal modulation.

11. The method of claim 1, wherein said modulated signal is the summation of two sinusoidal waveforms.

12. The method of claim 1, wherein said modulated signal uses a sawtooth or form of modulation.

13. The method of claim 1, wherein said modulated signal uses pseudo-random modulation.

14. In a packet network linking a sender and receiver, an apparatus for recovering timing information across the network at the receiver comprising:

a modulator at the sender for sending a modulated signal across the network conveying timing information; and

a clock recovery unit at the receiver using said modulated signal to improve the accuracy of the recovered clock.

15. The apparatus as claimed in claim 14, further comprising a control unit for varying the precise time of departure of outgoing packets to provide said modulated signal.

16. The apparatus as claimed in claim 15, wherein said recovery unit includes a synchronous detector for determining the precise time of arrival of an incoming packet.

17. The apparatus as claimed in claim 16, wherein the sender and receiver each include a local timebase as a reference.

18. The apparatus as claimed in claim 15, wherein said modulator is connected to a network interface unit.

19. The apparatus as claimed in claim 15, wherein said control unit varies the time of transmission of said packets to provide said offset.

20. The apparatus as claimed in claim 19, wherein said offset is an odd fraction f of a cycle of a clock signal wherein the timing error at the receiver contains only high frequency components.

21. The apparatus of claim 20, wherein the packet rate is offset by an amount equal to the ratio of the packet cycle and clock cycle multiplied by f.

22. The apparatus of claim 21, wherein f is {fraction (5/32)}.

23. The apparatus of claim 21, wherein f is {fraction (27/32)}.

24. The apparatus of claim 14 further comprising a phase locked loop at the receiver for removing errors arising in the last link of the network before the receiver.