METHOD OF MANUFACTURE OF RAISED SOURCE DRAIN MOSFET WITH TOP NOTCHED GATE STRUCTURE FILLED WITH DIELECTRIC PLUG IN AND DEVICE MANUFACTURED THEREBY

• US 20050054169A1
• Filed: 09/09/2003
• Published: 03/10/2005
• Est. Priority Date: 09/09/2003
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Wagner, Tina J., Rausch, Werner A., Deshpande, Sadanand V.
• Application Number:
  US10/605,100
• Publication Number:
  US 20050054169A1
• Time in Patent Office: Days
• US Class Current: 438/311
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A plug of dielectric material is formed in a notch in a cap layer above the gate polysilicon. The sidewalls of the gate electrode is covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

Claims

1. A method of forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer, wherein the gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer, comprising the steps of:

forming a cap layer over the gate electrode layer, forming a gate mask for patterning the gate electrode over said polysilicon, said mask covering a portion of said cap layer, and said mask having a pattern and having a periphery,

etching the cap layer in the pattern of the gate mask with the etching process undercutting below said cap layer under the periphery of the mask thereby forming a notch in the cap layer below the mask,

patterning the electrode stack by etching in said pattern of said gate mask,

filling the notch with dielectric plugs between the gate polysilicon and the sidewall spacers for the purpose of eliminating the exposure of the gate polysilicon,

forming said sidewall spacers reaching along the sidewalls of the gate electrode to above the level where said plugs contact the gate polysilicon, and

forming a raised source region and a raised drain region on top of said silicon layer aside from said spacers, whereby formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

2. The method of claim 1 wherein the cap layer comprises amorphous silicon formed by ion implantation of the polysilicon prior to forming the gate mask.

3. The method of claim 1 wherein said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

4. The method of claim 2 wherein said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

5. The method of claim 1 wherein

said gate mask comprises a hard mask, and

said cap layer comprises amorphous silicon formed by ion implantation of the polysilicon prior to forming the gate mask.

6. The method of claim 1 wherein

said gate mask comprises a hard mask, and

said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

7. The method of claim 6 wherein said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

8. The method of claim 1 wherein said cap layer is etched in the pattern of the mask. with a low pressure high bias etch forming said notch by said undercutting below said cap layer.

9. The method of claim 1 wherein

said cap layer is etched in the pattern of the mask. with a low pressure high bias etch forming said notch by said undercutting below said cap, and

then exposed surfaces of said cap layer are passivated by growing silicon oxide thereon.

10. The method of claim 1 wherein

said cap layer is etched in the pattern of the mask. with a low pressure high bias etch forming said notch by said undercutting below said cap,

then exposed surfaces of said cap layer are passivated by growing silicon oxide thereon, and

then said polysilicon and said gate dielectric are etched in a highly selective RTE process in the pattern of said mask.

11. A method of forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer, wherein the gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer, comprising the steps of:

forming a cap layer composed of amorphous silicon over the gate electrode layer,

forming a gate mask for patterning the gate electrode over said polysilicon, said mask covering a portion of said cap layer, and said mask having a pattern and having a periphery,

etching the cap layer in the pattern of the gate mask with the etching process undercutting below said cap layer under the periphery of the mask thereby forming a notch in the cap layer below the mask,

patterning the electrode stack by etching in said pattern of said gate mask,

filling the notch with dielectric plugs between the gate polysilicon and the sidewall spacers for the purpose of eliminating the exposure of the gate polysilicon,

forming said sidewall spacers reaching along the sidewalls of the gate electrode to above the level where said plugs contact the gate polysilicon, and

forming a raised source region and a raised drain region on top of said silicon layer aside from said spacers, whereby formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

12. The method of claim 11 wherein the amorphous silicon of said cap layer is formed by ion implantation of the polysilicon prior to forming the gate mask.

13. The method of claim 11 wherein said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

14. The method of claim 12 wherein said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

15. The method of claim 11 wherein

said gate mask comprises a hard mask, and

said cap layer comprises amorphous silicon formed by ion implantation of the polysilicon prior to forming the gate mask.

16. The method of claim 11 wherein

said gate mask comprises a hard mask, and

said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

17. The method of claim 16 wherein said dielectric plugs and said sidewall spacers are formed by forming a blanket layer of a dielectric material which is etched back to form said plugs and said sidewall spacers.

18. The method of claim 11 wherein said cap layer is etched in the pattern of the mask. with a low pressure high bias etch forming said notch by said undercutting below said cap layer.

19. The method of claim 11 wherein

said cap layer is etched in the pattern of the mask. with a low pressure high bias etch forming said notch by said undercutting below said cap, and

then exposed surfaces of said cap layer are passivated by growing silicon oxide thereon.

20. A SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer, wherein the gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer, comprising the steps of:

cap layer over the gate electrode layer,

a gate mask for patterning the gate electrode over said polysilicon, said mask covering a portion of said cap layer, and said mask having a pattern and having a periphery,

the cap layer being in the pattern of the gate mask with an undercut below said cap layer under the periphery of the mask in the form of a notch in the cap layer below the mask,

the notch being filled with dielectric plugs between the gate polysilicon and the sidewall spacers for the purpose of eliminating the exposure of the gate polysilicon,

said sidewall spacers reaching along the sidewalls of the gate electrode to above the level where said plugs contact the gate polysilicon, and

a raised source region and a raised drain region on top of said silicon layer aside from said spacers.