Method for forming ball pads of BGA substrate

• US 20050054187A1
• Filed: 09/03/2004
• Published: 03/10/2005
• Est. Priority Date: 09/05/2003
• Status: Abandoned Application

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Ding, Yi-Chuan, Ko, Shun-Fu
• Application Number:
  US10/933,350
• Publication Number:
  US 20050054187A1
• Time in Patent Office: Days
• US Class Current: 438/612
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/09436 Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/0969 Apertured conductors
• CPC Class Codes: H05K 2203/054 Continuous temporary metal layer over resist, e.g. for selective electroplating
• CPC Class Codes: H05K 3/061 Etching masks
• CPC Class Codes: H05K 3/062 consisting of metals or alloys or metallic inorganic compounds H05K3/065 takes precedence
• CPC Class Codes: H05K 3/3485 Applying solder paste, slurry or powder thick film methods for applying conductive paste or ink patterns H05K3/12
• CPC Class Codes: H05K 3/421 : Blind plated via connections H05K3/422, H05K3/423 and H05K3/425 take precedence

Abstract

A method for forming ball pads of a BGA substrate is disclosed. A substrate is provided with a plurality of pad terminals on its surface. A solder mask is formed on the surface and has a plurality of openings to expose the pad terminals. A metal layer for redefining ball pads is formed on the solder mask. An etching mask is formed on the metal layer, the etching mask has a plurality of covering portions which are aligned with the pad terminals and larger than the openings of the solder mask. The metal layer is etched to form a plurality of redefined ball pads under the etching mask. The redefined ball pads cover the pad terminals of the substrate and extend around the openings of the solder mask so that solder balls can be jointed with the redefined ball pads to avoid contacting the solder mask and the pad terminals by redefinition of bonding area of solder balls.

Claims

1. A method for forming ball pads of a BGA substrate, comprising:

providing a substrate, the substrate having a plurality of pad terminals and a solder mask on a surface, the solder mask having a plurality of openings to expose the pad terminals;

forming a metal layer on the solder mask, the metal layer covering the pad terminals via the openings;

forming an etching mask on the metal layer, the etching mask having a plurality of covering portions which are aligned with the pad terminals and are larger than the openings of the solder mask; and

etching the metal layer to form a plurality of redefined ball pads under the covering portions of the etching mask.

2. The method of claim 1, wherein the redefined ball pads extend onto the solder mask around the corresponding openings.

3. The method of claim 1, wherein the thickness of the redefined ball pads ranges between 3.0 and 5.0 μ

m.

4. The method of claim 1, wherein the metal layer is formed by electroless plating or sputtering.

5. The method of claim 1, wherein the redefined ball pads are made of the material containing copper.

6. The method of claim 1, wherein a Ni/Au layer is formed on the redefined ball pads.

7. The method of claim 1, wherein the etching mask is a dry film.

8. The method of claim 1, wherein the etching mask is a solder pattern.

9. The method of claim 8, wherein the solder pattern is formed on the metal layer by stencil printing or screen printing of a solder paste.

10. The method of claim 1, wherein the pad terminals are SMD (Solder Mask Defined) pads.

11. The method of claim 1, wherein the pad terminals are NSMD (Non-Solder Mask Defined) pads.

12. The method of claim 1, wherein each pad terminal has a central hole.

13. The method of claim 1, further comprising a plasma treatment on the solder mask.

14. A substrate for semiconductor package comprising:

a substrate having a surface;

a plurality of pad terminals are formed on the surface;

a solder mask formed on the surface, the solder mask having a plurality of openings to expose the pad terminals, and

a plurality of redefined ball pads covering the pad terminals via the openings, the redefined ball pads are larger than the openings of the solder mask.

15. The substrate of claim 14, wherein the redefined ball pads extend onto the solder mask around the corresponding openings

16. The substrate of claim 14, wherein the thickness of the redefined ball pads ranges between 3.0 μ

m and 5.0 μ

m.

17. The substrate of claim 14, wherein the redefined ball pads are made of the material containing copper.

18. The substrate of claim 14, further comprising a Ni/Au layer being formed on the redefined ball pads.

19. The substrate of claim 14, further comprising an etching mask being formed on the redefined ball pads.

20. The substrate of claim 14, wherein the etching mask is a solder pattern.

21. The substrate of claim 14, wherein the pad terminals are SMD (Solder Mask Defined) pads.

22. The substrate of claim 14, wherein the pad terminals are NSMD (Non-Solder Mask Defined) pads.

23. The substrate of claim 14, wherein each pad terminal has a central hole.