Intra-frequency searching in the presence of frequency gaps

• US 20050054368A1
• Filed: 08/27/2003
• Published: 03/10/2005
• Est. Priority Date: 08/27/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Amerga, Messay
• Granted Patent: US 7,917,163 B2
• Time in Patent Office: Days
• US Class Current: 455/525
• CPC Class Codes: H04W 36/00835 Determination of neighbour cell lists
• CPC Class Codes: H04W 36/0085 Hand-off measurements
• CPC Class Codes: H04W 48/20 Selecting an access point

Abstract

Techniques for intra-frequency searching in the presence of frequency gaps are disclosed. In one embodiment, a search is scheduled and frequency switches are suppressed during the scheduled search. In another embodiment, a search is scheduled in between anticipated frequency gaps. In yet another embodiment, a timer is deployed, the expiration of which indicates a search is to be scheduled. In yet another embodiment, a timer is deployed, the expiration of which indicates a search is to be scheduled and frequency switches are suppressed during the scheduled search. Various other embodiments are also presented. Benefits include allowing prescribed levels of intra-frequency and inter-frequency search to be performed which allows for improved base station selection and therefore improved performance and system capacity.

Claims

1. An apparatus, comprising:

a search scheduler for scheduling a search and for generating a frequency switch blocking signal; and

a frequency controller for generating frequency switch commands, receiving the frequency switch blocking signal, and suppressing the generation of frequency switch commands when the frequency switch blocking signal is asserted.

2. The apparatus of claim 1, further comprising a gap manager for indicating when a frequency switch is to occur, and wherein the search scheduler schedules the search during a period of time without a frequency switch as indicated by the gap manager.

3. The apparatus of claim 1, wherein the search scheduler comprises a timer, the expiration of which indicates a search is to be scheduled.

4. The apparatus of claim 3, wherein the search scheduler schedules a search without asserting the frequency switch blocking signal prior to the timer expiration.

5. The apparatus of claim 3, wherein the timer resets upon the completion of a scheduled search.

6. The apparatus of claim 3, wherein the search scheduler schedules a search and asserts the frequency switch blocking signal subsequent to the timer expiration.

7. The apparatus of claim 1, wherein the search scheduler asserts the frequency switch blocking signal during the scheduled search.

8. The apparatus of claim 2, wherein the search scheduler schedules a plurality of search types.

9. The apparatus of claim 8, wherein the search scheduler schedules one or more of the plurality of search types in response to the frequency switch indicator received from the gap manager.

10. The apparatus of claim 8, wherein the search scheduler comprises a plurality of timers corresponding to one or more of the plurality of search types, the expiration of each timer indicating a search of the respective search type is to be scheduled.

11. The apparatus of claim 10, wherein the search scheduler schedules a search corresponding to one of the plurality of search types and asserts the frequency switch blocking signal subsequent to the respective timer expiration.

12. The apparatus of claim 8, wherein the plurality of search types comprises one or more of a list search, a W-CDMA step one search, or a W-CDMA step two search.

13. A first Integrated Circuit (IC), responsive to a frequency switch signal generated in a second IC, the second IC comprising:

a search scheduler for scheduling a search and for generating a frequency switch blocking signal; and

a frequency controller for generating a frequency switch signal comprising frequency switch commands, receiving the frequency switch blocking signal, and suppressing the generation of frequency switch commands when the frequency switch blocking signal is asserted,

the first IC comprising;

a frequency synthesizer to receive the frequency switch signal from the second IC and to generate an output signal, the frequency of the output signal changing from a first frequency to a second frequency in response to the frequency switch signal.

14. A wireless communication device, comprising:

a processor for

scheduling a search;

generating a frequency switch blocking signal;

generating frequency switch commands; and

suppressing the generation of frequency switch commands when the frequency switch blocking signal is asserted.

15. The wireless communication device of claim 14, further comprising a frequency synthesizer to receive the frequency switch commands and to generate an output signal, the frequency of the output signal changing from a first frequency to a second frequency in response to the frequency switch commands.

16. The wireless communication device of claim 14, further comprising a searcher for searching in accordance with the scheduled search and for indicating to the search scheduler when the scheduled search is complete.

17. A method of searching in the presence of frequency gaps, comprising:

scheduling a search; and

suppressing frequency switches during the scheduled search.

18. The method of claim 17, further comprising:

determining future frequency switches; and

wherein the search is scheduled during a time period in which no future frequency switches are determined.

19. The method of claim 18, further comprising:

timing the duration between searches; and

scheduling searches without suppressing frequency switches prior to the timed duration reaching a pre-determined maximum.

20. An apparatus, comprising:

means for scheduling a search; and

means for suppressing frequency switches during the scheduled search.

21. Processor readable media operable to perform the following steps:

scheduling a search; and

suppressing frequency switches during the scheduled search.