Circuit operation verification device and method

• US 20050055190A1
• Filed: 09/08/2004
• Published: 03/10/2005
• Est. Priority Date: 09/09/2003
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hosokawa, Kohei
• Granted Patent: US 7,228,513 B2
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A circuit verification device includes emulators to which circuit portions obtained by dividing the circuit are implemented. The emulators communicate with each other through a bus to verify the functional operation of the circuit. The circuit is divided based on a communication occurrence pattern between circuit units so that the number of communications occurring between circuit portions is minimized. The input signals of the bus are preferably arranged in the bus address space in descending order of a signal change rate, and a burst transfer may be utilized. Through paths within the circuit being verified are searched, and a plurality of circuit units is divided so as to minimize the number of through paths among the circuit portions.

Claims

1. A circuit operation verification device for verifying by simulation a functional operation of a circuit to be verified, comprising:

a plurality of simulation sections for each simulating functional operations of a plurality of circuit portions into which the circuit is divided;

a bus for connecting the plurality of simulation sections to enable mutual communications;

a bus controller for controlling the bus; and

to a higher-level controller for controlling the bus controller for communications among the plurality of simulation sections to verify the functional operation of the circuit to be verified.

2. The circuit operation verification device according to claim 1, wherein any of the plurality of simulation sections and the bus controller is allowed to be a bus master for communications.

3. The circuit operation verification device according to claim 1, wherein the bus controller operates as a bus master, allowing any of the plurality of simulation sections to perform communication under control of the bus controller.

4. The circuit operation verification device according to claim 1, wherein each of the plurality of simulation sections arranges input signals from the bus and output signals to the bus in a bus address space in descending order of a signal change rate.

5. The circuit operation verification device according to claim 1, wherein input signals and output signals of each of the plurality of simulation sections are transmitted and received in burst transfer when signals to be transferred are placed at addresses in proximate to each other.

6. The circuit operation verification device according to claim 1, wherein signals of through paths existing among the plurality of simulation sections are bundled and placed in a portion of the bus address space in each of the plurality of simulation sections.

7. The circuit operation verification device according to claim 6, wherein the signals of the through paths are transferred in burst when the bus controller operates as a bus master.

8. The circuit operation verification device according to claim 1, wherein each of the plurality of simulation sections transmits and receives a signal that has been changed.

9. The circuit operation verification device according to claim 1, wherein the plurality of simulation sections includes at least one emulator to which a corresponding circuit portion of the circuit is implemented.

10. The circuit operation verification device according to claim 9, wherein each of the at least one emulator comprises:

a bus interface connected to the bus;

a programmable circuit for emulating an operation of the corresponding circuit portion of the circuit; and

a communication circuit for transferring a changed signal between the bus interface and the programmable circuit.

11. The circuit operation verification device according to claim 10, wherein the communication circuit comprises a register for retaining an input signal received from the bus interface.

12. The circuit operation verification device according to claim 10, wherein the communication circuit comprises a three-state buffer for transferring an output signal outputted from the programmable circuit to the bus interface, wherein the three-state buffer is provided by a programmable device.

13. The circuit operation verification device according to claim 1, wherein the plurality of simulation sections includes at least one simulator for simulating an operation of a corresponding circuit portion of the circuit by software.

14. The circuit operation verification device according to claim 1, wherein the circuit comprises a plurality of circuit units, each of which comprises at least one circuit element, wherein the plurality of circuit units is divided based on a temporal communication occurrence pattern among the plurality of circuit units so that the number of communications occurring among the plurality of simulation sections is minimized, to generate the plurality of simulation sections.

15. The circuit operation verification device according to claim 1, wherein the circuit comprises a plurality of circuit units, each of which comprises at least one circuit element, wherein the plurality of circuit units is divided so that the number of through paths among the plurality of simulation sections is minimized, to generate the plurality of simulation sections.

16. A circuit operation verification method for verifying by simulation a functional operation of a circuit to be verified, comprising:

a) dividing the circuit into a plurality of circuit portions so that the number of communications among the plurality of circuit portions is minimized when the circuit is divided into the plurality of circuit portions;

b) connecting a plurality of simulation circuits so as to enable mutual communication via a bus, wherein the plurality of simulation circuits each simulate functional operations of the plurality of circuit portions; and

c) verifying the functional operation of the circuit by communicating among the plurality of simulation circuits.

17. The circuit operation verification method according to claim 16, wherein step a) comprises:

a1) inputting a temporal communication occurrence pattern obtained from an arbitrary combination of a plurality of circuit units constituting the circuit; and

a2) dividing the plurality of circuit units into a plurality of circuit portions based on the temporal communication occurrence pattern of the plurality of circuit units so that the number of communications occurring among the plurality of circuit portions is minimized.

18. The circuit operation verification method according to claim 16, wherein, in step b), input signals from the bus and output signals to the bus in each of the plurality of simulation circuits are arranged in a bus address space in descending order of a signal change rate.

19. The circuit operation verification method according to claim 16, wherein, in step c), input signals and output signals of each of the plurality of simulation circuits are transmitted and received in burst transfer when signals to be transferred are placed at addresses in proximate to each other.

20. The circuit operation verification method according to claim 16, wherein step a) comprises:

a1) searching for through paths among a plurality of circuit units constituting the circuit; and

a2) dividing the plurality of circuit units into a plurality of circuit portions so that the number of through paths among the plurality of circuit portions is minimized.

21. The circuit operation verification method according to claim 20, wherein, in step b), signals of through paths existing among the plurality of simulation circuits are bundled and placed in a portion of the bus address space in each of the plurality of simulation circuits.

22. The circuit operation verification method according to claim 21, wherein, in step c), the signals of the through paths are transferred in burst.

23. The circuit operation verification method according to claim 16, wherein step c) comprises:

c.1) sequentially making the plurality of simulation circuits and a bus controller for controlling the bus a bus master;

c.2) at a simulation circuit that has become the bus master, transferring an output signal to another simulation circuit; and

c.3) at the bus controller that has become the bus master, setting the clock signal of each of the plurality of simulation circuits to active after determination of a break condition.

24. The circuit operation verification method according to claim 16, wherein step c) comprises:

c.1) at the bus controller for controlling the bus, setting transferred signals of the plurality of simulation circuits to the simulation circuits;

c.2) transferring signals on the through paths among the plurality of circuit units; and

c.3) at the bus controller, setting the clock signal, of each of the plurality of simulation circuits to active after determination of a break condition.

25. A computer-readable program for causing a computer to verify by simulation a functional operation of a circuit to be verified, comprising:

a) dividing the circuit into a plurality of circuit portions so that the number of communications among the plurality of circuit portions is minimized when the circuit is divided into the plurality of circuit portions;

b) connecting a plurality of simulation circuits so as to enable mutual communication via a bus, wherein the plurality of simulation circuits each simulate functional operations of the plurality of circuit portions; and

c) verifying the functional operation of the circuit by communicating among the plurality of simulation circuits.

26. The computer-readable program according to claim 25, wherein step a) comprises:

a1) inputting a temporal communication occurrence pattern obtained from an arbitrary combination of a plurality of circuit units constituting the circuit; and

a2) dividing the plurality of circuit units into a plurality of circuit portions based on the temporal communication occurrence pattern of the plurality of circuit units so that the number of communications occurring among the plurality of circuit portions is minimized.

27. The circuit operation verification program according to claim 25, wherein step a) comprises:

a1) searching for a through path among a plurality of circuit units constituting the circuit; and

a2) dividing the plurality of circuit units into a plurality of circuit portions so that the number of through paths among the plurality of circuit portions is minimized.

28. The circuit operation verification program according to claim 25, wherein step c) comprises:

c.1) sequentially making the plurality of simulation circuits and a bus controller for controlling the bus a bus master;

c.2) at a simulation circuit that has become the bus master, transferring an output signal to another simulation circuit; and

c.3) at the bus controller that has become the bus master, setting the clock signal of each of the plurality of simulation circuits to active after determination of a break condition.

29. The circuit operation verification program according to claim 25, wherein step c) comprises:

c.1) at the bus controller for controlling the bus, setting transferred signals of the plurality of simulation circuits to the simulation circuits;

c.2) transferring signals on the through paths among the plurality of circuit units; and

c.3) at the bus controller, setting the clock signal of each of the plurality of simulation circuits to active after determination of a break condition.