Compacting circuit responses
First Claim
1. A method of developing a response compactor comprising:
- adding at least two columns to a compactor matrix for each circuit output that can produce an unknown logic value at the same time.
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Abstract
A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.
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Citations
25 Claims
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1. A method of developing a response compactor comprising:
adding at least two columns to a compactor matrix for each circuit output that can produce an unknown logic value at the same time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A response compactor formed by the process including the steps of:
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obtaining a number of circuit outputs that can produce unknown logic values at the same time; and
adding at least two columns to a compactor matrix for each such circuit output that can produce unknown logic values at the same time. - View Dependent Claims (10, 11, 12, 13, 14, 15, 17, 18)
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16. A response compactor comprising:
a plurality of exclusive OR gates arranged to handle any number of scan chains with unknown logic values.
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19. An article comprising a medium storing instructions that, if executed, enable a processor-based system to:
add at least two columns to a compactor matrix for each scan chain that can produce an unknown logic value at the same time. - View Dependent Claims (20, 21, 22, 23, 24, 25)
Specification