Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

• US 20050055617A1
• Filed: 07/29/2004
• Published: 03/10/2005
• Est. Priority Date: 08/01/2003
• Status: Active Grant

• Current Assignee: Syntest Technologies Incorporated
• Original Assignee: Syntest Technologies Incorporated
• Inventors: Sheu, Boryau, Wang, Shun-Miin, Wu, Shianling, Wang, Laung-Terng, Kifli, Augusli, Wen, Xiaoqing, Hsu, Fei-Sheng, Lin, Shyh-Horng, Abdel-Hafez, Khader S., Chang, Ming-Tung
• Granted Patent: US 7,512,851 B2
• Time in Patent Office: Days
• US Class Current: 714/727
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture

Abstract

A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit'"'"'s test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division demultiplexors (TDDMs) 402, 403, decompressors 404, 405, compressors 406, 407, and time-division multiplexors (TDMs) 408, 409.

Claims

1. A method for time-division demultiplexing and decompressing a compressed input stimulus, provided at a selected data-rate R1, into a decompressed stimulus, driven at a selected data-rate R2, for driving selected scan chains in a scan-based integrated circuit during scan-test mode, the scan-based integrated circuit containing a plurality of time-division demultiplexors (TDDMs), a plurality of decompressors, a plurality of compressors, a plurality of time-division multiplexors (TDMs), at least one high-speed clock CK1, at least one low-speed clock CK2, and a plurality of scan chains, each scan chain comprising multiple scan cells coupled in series;

said method comprising;

(a) generating, shifting in, demultiplexing and decompressing said compressed input stimulus through said time-division demultiplexors and said decompressors as said decompressed stimulus to all said scan cells in said scan-based integrated circuit during a shift-in operation;

(b) capturing a test response to all said scan cells during a selected capture operation;

(c) compressing, multiplexing and shifting out said test response or said decompressed stimulus through said compressors and said time-division multiplexors as a compressed test response, while shifting in a new decompressed stimulus to all said scan cells, during a shift-out operation; and

(d) repeating steps (b) to (c) until a predetermined criterion is reached.

2. The method of claim 1, wherein said high-speed clock CK1 is supplied externally from an automatic test equipment (ATE).

3. The method of claim 1, wherein said high-speed clock CK1 is generated internally using a first phase-locked loop (PLL).

4. The method of claim 1, wherein said high-speed clock CK1 is generated internally from said low-speed clock CK2.

5. The method of claim 1, wherein said low-speed clock CK2 is supplied externally from said automatic test equipment (ATE).

6. The method of claim 1, wherein said low-speed clock CK2 is generated internally using a second phase-locked loop (PLL).

7. The method of claim 1, wherein said low-speed clock CK2 is generated internally from said high-speed clock CK1.

8. The method of claim 1, wherein said selected data-rate R1 is a greater-than-one integer multiple of said selected data-rate R2.

9. The method of claim 1, wherein said high-speed clock CK1 is used to sample said compressed input stimulus in said time-division demultiplexor (TDDM);

wherein said selected data-rate R1 matches the frequency of said high-speed clock CK1.

10. The method of claim 9, wherein said time-division demultiplexor (TDDM) is a shift register driven by said high-speed clock CK1.

11. The method of claim 1, wherein said low-speed clock CK2 is used to control all said scan cells in said selected scan chains for driving said decompressed stimulus and said test responses into and out of said selected scan chains through said decompressors and said compressors, respectively;

wherein said selected data-rate R2 matches the frequency of said low-speed clock CK2.

12. The method of claim 1, wherein said high-speed clock CK1 is used to control said time-division multiplexor (TDM) for generating said compressed test response operating at said selected data-rate R1;

wherein said selected data-rate R1 matches the frequency of said high-speed clock CK1.

13. The method of claim 12, wherein said time-division multiplexor (TDM) further comprises a multiplexor and a controller driven by said high-speed clock CK1.

14. The method of claim 1, wherein said time-division demultiplexor (TDDM) further comprises one or more first selected combinational logic gates operating at said selected data-rate R1;

wherein each said first selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

15. The method of claim 1, wherein said time-division demultiplexor (TDDM) further comprises one or more first selected sequential logic gates driven by said high-speed clock CK1;

wherein each said first selected sequential logic gate is selectively a flip-flop or a latch.

16. The method of claim 1, wherein said decompressor is a broadcaster comprising one or more second selected combinational logic gates operating at said selected data-rate R2;

wherein each said second selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

17. The method of claim 1, wherein said decompressor is a linear finite-state machine (LFSM) comprising one or more second selected sequential logic gates driven by said low-speed clock CK2;

wherein each said second selected sequential logic gate is selectively a flip-flop or a latch.

18. The method of claim 1, wherein said compressor is a compactor comprising one or more third selected combinational logic gates operating at said selected data-rate R2;

wherein each said third selected combinational logic gate is selectively an Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, buffer (BUF), or inverter (INV).

19. The method of claim 1, wherein said compressor is a multiple-input signature register (MISR) comprising one or more third selected sequential logic gates driven by said low-speed clock CK2;

wherein each said fourth selected sequential logic gate is selectively a flip-flop or a latch.

20. The method of claim 1, wherein said time-division multiplexor (TDM) further comprises one or more fourth selected combinational logic gates operating at said selected data-rate R1;

wherein each said fourth selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

21. The method of claim 1, wherein said time-division multiplexor (TDM) further comprises one or more fourth selected sequential logic gates driven by said high-speed clock CK1;

wherein each said fourth selected sequential logic gate is selectively a flip-flop or a latch.

22. The method of claim 1, wherein said decompressor and said compressor are selectively pipelined and embedded between said scan cells to allow said shift-in operation and said shift-out operation to be performed at high speed, respectively.

23. The method of claim 1, wherein said decompressor is selectively placed before said time-division demultiplexor (TDDM);

wherein said decompressor is driven by said high-speed clock CK1.

24. The method of claim 1, wherein said compressor is selectively placed after said time-division multiplexor (TDM);

wherein said compressor is driven by said high-speed clock CK1.

25. An apparatus for time-division demultiplexing and decompressing a compressed input stimulus, provided at a selected data-rate R1, into a decompressed stimulus, driven at a selected data-rate R2, for driving selected scan chains in a scan-based integrated circuit during scan-test mode, the scan-based integrated circuit containing at least one high-speed clock CK1, at least one low-speed clock CK2, and a plurality of scan chains, each scan chain comprising multiple scan cells coupled in series;

said apparatus comprising;

(a) a plurality of time-division demultiplexors (TDDMs);

(b) a plurality of decompressors;

(c) a plurality of compressors; and

(d) a plurality of time-division multiplexors (TDMs).

26. The apparatus of claim 25, wherein said high-speed clock CK1 is supplied externally from an automatic test equipment (ATE).

27. The apparatus of claim 25, wherein said high-speed clock CK1 is generated internally using a first phase-locked loop (PLL).

28. The apparatus of claim 25, wherein said high-speed clock CK1 is generated internally from said low-speed clock CK2.

29. The apparatus of claim 25, wherein said low-speed clock CK2 is supplied externally from said automatic test equipment (ATE).

30. The apparatus of claim 25, wherein said low-speed clock CK2 is generated internally using a second phase-locked loop (PLL).

31. The apparatus of claim 25, wherein said low-speed clock CK2 is generated internally from said high-speed clock CK1.

32. The apparatus of claim 25, wherein said selected data-rate R1 is a greater-than-one integer multiple of said selected data-rate R2.

33. The apparatus of claim 25, wherein said high-speed clock CK1 is used to sample said compressed input stimulus in said time-division demultiplexor (TDDM);

wherein said selected data-rate R1 matches the frequency of said high-speed clock CK1.

34. The apparatus of claim 33, wherein said time-division demultiplexor (TDDM) is a shift register driven by said high-speed clock CK1.

35. The apparatus of claim 25, wherein said low-speed clock CK2 is used to control all said scan cells in said selected scan chains for driving said decompressed stimulus and said test responses into and out of said selected scan chains through said decompressors and said compressors, respectively;

wherein said selected data-rate R2 matches the frequency of said low-speed clock CK2.

36. The apparatus of claim 25, wherein said high-speed clock CK1 is used to control said time-division multiplexor (TDM) for generating said compressed test response operating at said selected data-rate R1;

wherein said selected data-rate R1 matches the frequency of said high-speed clock CK1.

37. The apparatus of claim 36, wherein said time-division multiplexor (TDM) further comprises a multiplexor and a controller driven by said high-speed clock CK1.

38. The apparatus of claim 25, wherein said time-division demultiplexor (TDDM) further comprises one or more first selected combinational logic gates operating at said selected data-rate R1;

wherein each said first selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

39. The apparatus of claim 25, wherein said time-division demultiplexor (TDDM) further comprises one or more first selected sequential logic gates driven by said high-speed clock CK1;

wherein each said first selected sequential logic gate is selectively a flip-flop or a latch.

40. The apparatus of claim 25, wherein said decompressor is a broadcaster comprising one or more second selected combinational logic gates operating at said selected data-rate R2;

wherein each said second selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

41. The apparatus of claim 25, wherein said decompressor is a linear finite-state machine (LFSM) comprising one or more second selected sequential logic gates driven by said low-speed clock CK2;

wherein each said second selected sequential logic gate is selectively a flip-flop or a latch.

42. The apparatus of claim 25, wherein said compressor is a compactor comprising one or more third selected combinational logic gates operating at said selected data-rate R2;

wherein each said third selected combinational logic gate is selectively an Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, buffer (BUF), or inverter (INV).

43. The apparatus of claim 25, wherein said compressor is a multiple-input signature register (MISR) comprising one or more third selected sequential logic gates driven by said low-speed clock CK2;

wherein each said fourth selected sequential logic gate is selectively a flip-flop or a latch.

44. The apparatus of claim 25, wherein said time-division multiplexor (TDM) further comprises one or more fourth selected combinational logic gates operating at said selected data-rate R1;

wherein each said fourth selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

45. The apparatus of claim 25, wherein said time-division multiplexor (TDM) further comprises one or more fourth selected sequential logic gates driven by said high-speed clock CK1;

wherein each said fourth selected sequential logic gate is selectively a flip-flop or a latch.

46. The apparatus of claim 25, wherein said decompressor and said compressor are selectively pipelined and embedded between said scan cells to allow said shift-in operation and said shift-out operation to be performed at high speed, respectively.

47. The apparatus of claim 25, wherein said decompressor is selectively placed before said time-division demultiplexor (TDDM);

wherein said decompressor is driven by said high-speed clock CK1.

48. The apparatus of claim 25, wherein said compressor is selectively placed after said time-division multiplexor (TDM);

wherein said compressor is driven by said high-speed clock CK1.

49. A method for synthesizing an apparatus for time-division demultiplexing and decompressing a compressed input stimulus, provided at a selected data-rate R1, into decompressed stimulus, driven at a selected data-rate R2, for driving selected scan chains in a scan-based integrated circuit during scan-test mode, the scan-based integrated circuit containing a plurality of time-division demultiplexors (TDDMs), a selected plurality of decompressors, a selected plurality of compressors, a plurality of time-division multiplexors (TDMs), at least one high-speed clock CK1, at least one low-speed clock CK2, and a plurality of scan chains, each scan chain comprising multiple scan cells coupled in series;

said method comprising the computer-implemented steps of;

(a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;

(b) specifying input constraints on said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs);

(c) synthesizing said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs) on said design database according to said input constraints; and

(d) generating synthesized HDL code for said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs) in a selected RTL or gate-level format.

50. The method of claim 49, wherein said specifying input constraints further comprises automatically generating said input constraints based on said design database.

51. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said high-speed clock CK1 to be supplied externally from an automatic test equipment (ATE).

52. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said high-speed clock CK1 to be generated internally using a first phase-locked loop (PLL).

53. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said high-speed clock CK1 to be generated internally from said low-speed clock CK2.

54. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said low-speed clock CK2 to be supplied externally from said automatic test equipment (ATE).

55. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said low-speed clock CK2 to be generated internally using a second phase-locked loop (PLL).

56. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said low-speed clock CK2 to be generated internally from said high-speed clock CK1.

57. The method of claim 49, wherein said synthesizing said plurality of time-division demultiplexors (TDDMs) further comprises synthesizing said selected data-rate R1 to be a greater-than-one integer multiple of said selected data-rate R2.

58. The method of claim 49, wherein said high-speed clock CK1 is used to sample said compressed input stimulus in said time-division demultiplexor (TDDM);

wherein said selected data-rate R1 matches the frequency of said high-speed clock CK1.

59. The method of claim 58, wherein said time-division demultiplexor (TDDM) is a shift register driven by said high-speed clock CK1.

60. The method of claim 49, wherein said low-speed clock CK2 is used to control all said scan cells in said selected scan chains for driving said decompressed stimulus and said test responses into and out of said selected scan chains through said decompressors and said compressors, respectively;

wherein said selected data-rate R2 matches the frequency of said low-speed clock CK2.

61. The method of claim 49, wherein said high-speed clock CK1 is used to control said time-division multiplexor (TDM) for generating said compressed test response operating at said selected data-rate R1;

wherein said selected data-rate R1 matches the frequency of said high-speed clock CK1.

62. The method of claim 61, wherein said time-division multiplexor (TDM) further comprises a multiplexor and a controller driven by said high-speed clock CK1.

63. The method of claim 49, wherein said time-division demultiplexor (TDDM) further comprises one or more first selected combinational logic gates operating at said selected data-rate R1;

wherein each said first selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

64. The method of claim 49, wherein said time-division demultiplexor (TDDM) further comprises one or more first selected sequential logic gates driven by said high-speed clock CK1;

wherein each said first selected sequential logic gate is selectively a flip-flop or a latch.

65. The method of claim 49, wherein said decompressor is a broadcaster comprising one or more second selected combinational logic gates operating at said selected data-rate R2;

wherein each said second selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

66. The method of claim 49, wherein said decompressor is a linear finite-state machine (LFSM) comprising one or more second selected sequential logic gates driven by said high-speed clock CK2;

wherein each said second selected sequential logic gate is selectively a flip-flop or a latch.

67. The method of claim 49, wherein said compressor is a compactor comprising one or more third selected combinational logic gates operating at said selected data-rate R2;

wherein each said third selected combinational logic gate is selectively an Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, buffer (BUF), or inverter (INV).

68. The method of claim 49, wherein said compressor is a multiple-input signature register (MISR) comprising one or more third selected sequential logic gates driven by said low-speed clock CK2;

wherein each said fourth selected sequential logic gate is selectively a flip-flop or a latch.

69. The method of claim 49, wherein said time-division multiplexor (TDM) further comprises one or more fourth selected combinational logic gates operating at said selected data-rate R1;

wherein each said fourth selected combinational logic gate is selectively an AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR (XOR) gate, Exclusive-NOR (XNOR) gate, multiplexor (MUX), buffer (BUF), or inverter (INV).

70. The method of claim 49, wherein said time-division multiplexor (TDM) further comprises one or more fourth selected sequential logic gates driven by said high-speed clock CK1;

wherein each said fourth selected sequential logic gate is selectively a flip-flop or a latch.

71. The method of claim 49, wherein said decompressor and said compressor are selectively pipelined and embedded between said scan cells to allow said shift-in operation and said shift-out operation to be performed at high speed, respectively.

72. The method of claim 49, wherein said decompressor is selectively placed before said time-division demultiplexor (TDDM);

wherein said decompressor is driven by said high-speed clock CK1.

73. The method of claim 49, wherein said compressor is selectively placed after said time-division multiplexor (TDM);

wherein said compressor is driven by said high-speed clock CK1.

74. A computer-readable memory having computer-readable program code embodied therein for causing a computer system to perform a method for synthesizing an apparatus for time-division demultiplexing and decompressing a compressed input stimulus, provided at a selected data-rate R1, into decompressed stimulus, driven at a selected data-rate R2, for driving selected scan chains in a scan-based integrated circuit during scan-test mode, the scan-based integrated circuit containing a plurality of time-division demultiplexors (TDDMs), a selected plurality of decompressors, a selected plurality of compressors, a plurality of time-division multiplexors (TDMs), at least one high-speed clock CK1, at least one low-speed clock CK2, and a plurality of scan chains, each scan chain comprising multiple scan cells coupled in series;

said method comprising the computer-implemented steps of;

(a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;

(b) specifying input constraints on said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs);

(c) synthesizing said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs) on said design database according to said input constraints; and

(d) generating synthesized HDL code for said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs) in a selected RTL or gate-level format.

75. An electronic design automation system comprising:

a processor;

a bus coupled to said processor; and

a computer-readable memory coupled to said bus and having computer-readable program code embodied therein for causing said electronic design automation system to perform a method for synthesizing an apparatus for time-division demultiplexing and decompressing a compressed input stimulus provided at a selected data-rate R1, into decompressed stimulus driven at a selected data-rate R2, for driving selected scan chains in a scan-based integrated circuit during scan-test mode, the scan-based integrated circuit containing a plurality of time-division demultiplexors (TDDMs), a selected plurality of decompressors, a selected plurality of compressors, a plurality of time-division multiplexors (TDMs), at least one high-speed clock CK1, at least one low-speed clock CK2, and a plurality of scan chains, each scan chain comprising multiple scan cells coupled in series;

said method comprising the computer-implemented steps of;

(a) compiling the HDL (hardware description language) code modeled at RTL (register-transfer level) or at gate-level that represents said scan-based integrated circuit into a design database;

(b) specifying input constraints on said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs);

(c) synthesizing said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs) on said design database according to said input constraints; and

(d) generating synthesized HDL code for said plurality of time-division demultiplexors (TDDMs), said selected plurality of decompressors, said selected plurality of compressors, and said plurality of time-division multiplexors (TDMs) in a selected RTL or gate-level format.

76. A method for reducing test time, test data volume, and scan pin count for a scan-based integrated circuit, the scan-based integrated circuit containing a plurality of high-speed I/O pads and a plurality of scan chains, each scan chain comprising multiple scan cells coupled in series;

said method comprising

(a) providing time-division demultiplexor and multiplexor pairs for allowing scan data transfer between selected high-speed I/O pads and selected scan chains in said scan-based integrated circuit during test; and

(b) using decompressor and compressor pairs to perform scan compression and using said time-division demultiplexor and multiplexor pairs to operate said selected I/O pads at high speed, while operating said selected scan chains at low speed.

77. The method of claim 76, wherein said high-speed I/O pad is a high-speed I/O core pin embedded in said scan-based integrated circuit.