Method, system, and apparatus for bit error capture and analysis for serial interfaces

• US 20050055619A1
• Filed: 08/15/2003
• Published: 03/10/2005
• Est. Priority Date: 08/15/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bedwani, Serge
• Granted Patent: US 7,165,195 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

An apparatus and method to facilitate validation and/or test of serial interfaces by analyzing error event types based at least in part on a code-stamp, compare engine logic and a memory for error capture.

Claims

1. A method for testing comprising:

code stamping a plurality of data and transmitting the plurality of data;

receiving the plurality of data and code stamping the plurality of data;

comparing the received plurality of data to a plurality of expected data; and

creating an entry if there is a miscompare between the received data and expected data.

2. The method of claim 1 wherein the transmitting or receiving of the plurality of data is via a serial interface.

3. The method of claim 1 wherein the plurality of expected data is stored in a random access memory or a linear feedback shift register.

4. The method of claim 1 wherein the entry comprises the code stamp of the plurality of data that was received and the plurality of expected data and the received plurality of data.

5. An apparatus comprising

a compare logic;

at least one data recovery circuit and a code stamp counter coupled to the compare logic; and

a memory to store a plurality of expected data, coupled to the error capture and the compare logic, the apparatus to compare the plurality of expected data to a plurality of received data that is received by the data recovery circuit and to create a first entry in the event of a first miscompare.

6. The apparatus of claim 5 wherein the code stamp counter is to code stamp the plurality of received data.

7. The apparatus of claim 5 wherein the apparatus is a serial interface.

8. The apparatus of claim 6 wherein the entry comprises the code stamp of the plurality of received data, the plurality of expected data, and the plurality of received data.

9. The apparatus of claim 5 wherein the plurality of expected data is stored in a random access memory or a linear feedback shift register.

10. The apparatus of claim 9 wherein the compare logic is to receive the plurality of expected data from either the random access memory or the linear feedback shift register via a multiplexer.

11. The apparatus of claim 9 wherein the compare logic is to receive the plurality of received data from a receive first in first out (FIFO) memory.

12. The apparatus of claim 5 wherein the memory is to create a second entry in the event of a second miscompare.

13. The apparatus of claim 12 wherein the second entry is stored consecutively with the first entry in the memory.

14. The apparatus of claim 13 wherein subsequent miscompare events do not result in an entry being created in memory, but a third entry is created in memory for a successful comparision.

15. An apparatus comprising

a compare logic;

a code stamp counter coupled to the compare logic; and

a memory to store a plurality of expected data, coupled to the compare logic, the apparatus to compare the plurality of expected data to a plurality of received data that is received by the apparatus and to create;

a first entry in the memory in the event of a first miscompare between the plurality of expected data and the plurality of received data;

a second entry in the memory, consecutive to the first entry, based at least in type on a type of error event.

16. The apparatus of claim 15 wherein the code stamp counter is to code stamp the plurality of received data.

17. The apparatus of claim 15 wherein the apparatus is a serial interface.

18. The apparatus of claim 15 wherein the first entry comprises the code stamp of the plurality of received data, the plurality of expected data, and the plurality of received data.

19. The apparatus of claim 15 wherein the plurality of expected data is stored in a random access memory or a linear feedback shift register.

20. The apparatus of claim 19 wherein the compare logic is to receive the plurality of expected data from either the random access memory or the linear feedback shift register via a multiplexer.

21. The apparatus of claim 19 wherein the compare logic is to receive the plurality of received data from a receive first in first out (FIFO) memory.

22. The apparatus of claim 15 wherein the memory is to create a second entry in the event of a second miscompare for a burst-error event type.

23. The apparatus of claim 22 wherein the second entry is stored consecutively with the first entry in the memory.

24. The apparatus of claim 23 wherein subsequent miscompare events do not result in an entry being created in memory, but a third entry is created in memory for a successful comparision.

25. The apparatus of claim 15 wherein the memory is to create a second entry in the absence of a miscompare event of a for a single-error event type.

26. The apparatus of claim 25 wherein the second entry is stored consecutively with the first entry in the memory.