System on a chip bus with automatic pipeline stage insertion for timing closure

• US 20050055655A1
• Filed: 10/22/2004
• Published: 03/10/2005
• Est. Priority Date: 10/03/2002
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Wolford, Barry Joe, Drerup, Bernard Charles, Hofmann, Richard Gerard, Dieffenderfer, James Norris, Sartorius, Thomas Andrew, Augsburg, Victor Roberts
• Granted Patent: US 7,296,175 B2
• Time in Patent Office: Days
• US Class Current: 716/113
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.

Claims

1. A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies, said method comprising:

designing a layout of the chip with specific placement of devices, including a bus controller, a signal source device, and a destination device;

providing a set of said devices, which contain logic to control a protocol that functions with a plurality of latencies;

determining a time for a signal to propagate from the source device to the destination device relative to a default propagation time; and

inserting a pipeline stage in a bus path between said source device and said destination device for each additional time the signal takes to propagate.

2. The method of claim 1, wherein said default propagation time is set to one clock cycle.

3. The method of claim 1, wherein said designing step comprises selecting a processor local bus (PLB)5 macro as said bus controller with associated PLB5 operating protocol.

4. The method of claim 1, wherein said pipeline stage including in said step is a register.

5. The method of claim 1, wherein said source device and said destination device are respectively one of an initiator and a target.

6. The method of claim 1, further comprising:

identifying a first signal that does not meet a default timing requirement of the SoC operating parameters;

identifying other signals associated with said first signal that are required to complete a functional operation that involves said first signal; and

applying said inserting step to each of said signal and said other related signals wherein necessary pipeline stages are inserted in a path of each signal.

7. The method of claim 1, further comprising inserting a pipeline stage within said bus controller within particular ones of said signal path that require an additional pipeline stage.

8. The method of claim 1, wherein said determining step comprises evaluating a plurality of metrics including distance, wire dimensions and propagation characteristics, and chip fabrication technology.

9. The method of claim 3, wherein utilization of PLB5 Macro provides additional functional features, said method further comprising:

enabling an assertion of multiple write grant responses for multiple write requests in a pipelined manner from a source (target) device to a destination (initiator) device before all of write data is received at the target; and

enabling an assertion of a single write grant response for all write data associated with a single write request.

10. The method of claim 3, further comprising:

enabling an overlap of sequences by pulsing a control signal active on adjacent clock cycles for each of the protocol sequences, wherein a path that is more than one cycle in length is pipelined utilizing each register within the path for each additional clock cycle the signal takes to propagate to launch a different sequence.

11. A system on a chip designed according to claim 1.

12. A system on a chip (SoC) comprising:

a plurality of devices including an initiator and a target;

a bus controller interconnected with said initiator and said target;

wherein said bus controller is interconnected via a plurality of buses;

wherein said plurality of devices and said bus controller contain logic to control a protocol that functions with a plurality of latencies; and

wherein each of said plurality of buses on which a signal takes longer than a predetermined default number of clock cycles to propagate includes a pipeline stage for each additional clock cycle more than the default number required for the signal to propagate.

13. The SoC of claim 12, wherein said bus controller is a processor local bus (PLB)5 Macro.

14. The SoC of claim 13, further comprising a pipeline stage within said PLB Macro for particular paths where an additional pipeline stage is required.

15. The SoC of claim 13, wherein said pipeline stage is a register.

16. The SoC of claim 12, further comprising:

means for asserting multiple write grant responses for multiple write requests in a pipelined manner from a source device to a destination (initiator) device before all of write data is received at the target.

17. The SoC of claim 12, further comprising:

means for asserting a single write grant response for all write data associated with a single write request.

18. The SoC of claim 12, further comprising:

means for overlapping sequences by pulsing a control signal active on adjacent clock cycles for each of the protocol sequences, wherein a path that is more than one cycle in length is pipelined utilizing each register within the path for additional clock cycle the signal takes to propagate to launch a different sequence.

19. The SoC of claim 12, wherein the default number of clock cycles is 1.

20. The SoC of claim 12, wherein said logic to control a protocol that functions with a plurality of latencies further supports said protocol when said pipeline stages are inserted within said plurality of buses.